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169
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230
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An enhanced access and cycle time model for on-chip caches
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86
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Complexity/Performance Tradeoffs with Non-Blocking Loads
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339
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Limits of instruction-level parallelism
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16
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Design Considerations in Dynamically Scheduled Processors
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67
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Efficient Procedure Mapping using Cache Line Coloring
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40
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Software Methods for System Address Tracing: Implementation and Validation
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19
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The USENET Cookbook: an experiment in electronic publishing
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24
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Cache Coherence in Distributed Systems
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9
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Boiling Enhancement Techniques for Water at Low Pressure
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27
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Packaging a 150 W Bipolar ECL Microprocessor
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122
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Cache Write Policies and Performance
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90
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Link-Time Optimization of Address Calculation on a 64-bit Architecture
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61
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SCHEME->C: a Portable Scheme-to-C Compiler
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192
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Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines
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27
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MultiTitan: Four Architecture Papers
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13
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Boiling on Small Heat Dissipating Elements in Water at Subatmospheric Pressure
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32
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Interleaved Fin Thermal Connectors for Multichip Modules
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