Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation (1997)

by Chung-ping Chen , Chris C. N. Chu , D. F. Wong
Venue:In Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Citations:80 - 8 self

Active Bibliography

5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
103 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
7 Theory and Algorithm of Local-Refinement Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
7 Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
45 Closed form solution to simultaneous buffer insertion/sizing and wire sizing – Chris C. N. Chu, D. F. Wong - 1997
69 An Interconnect-Centric Design Flow for Nanometer Technologies – Jason Cong - 1999
11 An efficient and optimal algorithm for simultaneous buffer and wire sizing – Chris C. N. Chu, D. F. Wong - 1999
11 Greedy wire-sizing is linear time – Chris C. N. Chu, Martin D. F. Wong - 1998
1 Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design – Jason Cong - 1997
7 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs – Jason Cong, Lei He - 1997
9 A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing – Chris C. N. Chu, D. F. Wong - 1999
42 Optimal Wiresizing for Interconnects with Multiple Sources – Jason Cong, Lei He - 1996
6 Simultaneous Transistor and Interconnect Sizing Using General Dominance Property – Jason Cong, Lei He - 1995
13 A new approach to simultaneous buffer insertion and wire sizing – Chris C. N. Chu, D. F. Wong - 1997
A New Approach toSimultaneous Bu er Insertion and Wire Sizing – Chris C. N. Chu, D. F. Wong
66 Interconnect design for deep submicron ICs – Jason Cong, Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo - 1997
16 An Efficient Approach To Simultaneous Transistor And Interconnect Sizing – Jason Cong, Lei He - 1996
5 A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing – Chris C. N. Chu, et al.
27 Digital Circuit Optimization via Geometric Programming – Stephen P. Boyd, Seung-jean Kim, Dinesh D. Patil, Mark A. Horowitz - 2005