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48
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Optimal Wiresizing Under the Distributed Elmore Delay Model
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38
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High-Performance Routing Trees With Identified Critical Sinks
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49
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Simulataneous Driver and Wire Sizing for Performance and Power Optimization
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91
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Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model
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26
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A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-Driven Global Routing
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41
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27
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24
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10
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382
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43
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- 1996
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24
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Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
– C P Chen, Y W Chang, D F Wong
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16
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A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies
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51
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Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization
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