Optimal Wiresizing for Interconnects with Multiple Sources (1996)

by Jason Cong , Lei He
Venue:ACM Trans. on Design Automation of Electronics Systems
Citations:42 - 18 self

Active Bibliography

109 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
6 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
76 An Interconnect-Centric Design Flow for Nanometer Technologies – Jason Cong - 1999
72 Interconnect design for deep submicron ICs – Jason Cong, Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo - 1997
12 Performance Driven Global Routing for Standard Cell Design – Jason Cong, Patrick H. Madden - 1997
25 Interconnect Layout Optimization under Higher-Order RLC Model for MCM Designs – Jason Cong, Cheng-Kok Koh, Patrick H. Madden - 1997
30 Interconnect Performance Estimation Models for Design Planning – Jason Cong, Zhigang (David) Pan - 2001
1 Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design – Jason Cong - 1997
64 Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization – Takumi Okamoto , Jason Cong - 1996