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Incorporating Timing Constraints in the Efficient Memory Model for Symbolic Ternary Simulation
– Incorporating Timing Constraints, Miroslav N. Velev, Randal E. Bryant
- 1998
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3
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Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
– Miroslav N. Velev, Randal E. Bryant
- 1998
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4
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Verification of Pipelined Microprocessors by Comparing Memory Execution Sequences in Symbolic Simulation
– Randal E. Bryant
- 1997
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10
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Efficient Modeling of Memory Arrays in Symbolic Simulation
– Miroslav N. Velev
- 1997
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16
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Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking
– Miroslav N. Velev
- 1998
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19
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Formal Hardware Verification By Symbolic Trajectory Evaluation
– Alok Jain
- 1997
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25
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An industrially effective environment for formal hardware verification
– Carl-johan H. Seger, Robert B. Jones, John W. O’leary, Tom Melham, Mark D. Aagaard, Clark Barrett, Don Syme, An Industrially Effective Environment, {carl-johan H. Seger, Robert B. Jones, John W. O'leary, Tom Melham, Mark D. Aagaard, Clark Barrett, Don Syme, Mark D. Aagaard, Clark Barrett, Don Syme
- 2005
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2
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Integrating formal verification into an advanced computer architecture course
– Miroslav N. Velev
- 2003
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13
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Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs
– Miroslav N. Velev
- 2003
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11
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Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors
– Miroslav N. Velev, Randal E. Bryant
- 1999
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1
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Combining ATPG and symbolic simulation for efficient validation of embedded array systems
– Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-c. Wang, Kwang-ting (tim Cheng, Magdy S. Abadir
- 2002
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6
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Verifying Nondeterministic Implementations of Deterministic Systems
– Alok Jain, Kyle Nelson, Randal E. Bryant
- 1996
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1
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TLSim and EVC: a term-level symbolic simulator and an efficient decision procedure for the logic of equality with uninterpreted functions and memories
– Miroslav N. Velev, Randal E. Bryant
- 2005
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26
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Symbolic Trajectory Evaluation
– Scott Hazelhurst, Carl-johan H. Seger
- 1996
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9
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Formal verification of an ARM processor
– Vishnu A. Patankar, Alok Jain, Randal E. Bryant
- 1999
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6
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Can American Checkers be Solved by Means of Symbolic Model Checking?
– Michael Baldamus, Klaus Schneider, Michael Wenz, Roberto Ziller
- 2000
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3
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Digital Circuit Verification using Partially-Ordered State Models
– Randal E. Bryant, Carl-johan H. Seger
- 1994
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24
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Formally Verifying a Microprocessor Using a Simulation Methodology
– Derek L. Beatty, Randal E. Bryant
- 1994
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90
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Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories
– Carl-johan H. Seger, Randal E. Bryant
- 1993
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