Interconnect Estimation and Planning for Deep Submicron Designs (1998)

by Jason Cong , David Zhigang Pan
Venue:IN PROC. DESIGN AUTOMATION CONF
Citations:25 - 18 self

Active Bibliography

6 Wire Width Planning for Interconnect Performance Optimization – Jason Cong, Zhigang (David) Pan - 2002
5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
22 Interconnect Performance Estimation Models for Design Planning – Jason Cong, Zhigang (David) Pan - 2001
7 Theory and Algorithm of Local-Refinement Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
7 Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
7 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs – Jason Cong, Lei He - 1997
8 Interconnect Performance Estimation Models for Synthesis and Design Planning – Jason Cong , Zhigang Pan
103 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
69 An Interconnect-Centric Design Flow for Nanometer Technologies – Jason Cong - 1999
45 Closed form solution to simultaneous buffer insertion/sizing and wire sizing – Chris C. N. Chu, D. F. Wong - 1997
38 GLOBAL INTERCONNECT SIZING AND SPACING WITH CONSIDERATION OF COUPLING CAPACITANCE – Jason Cong, et al. - 1997
9 A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing – Chris C. N. Chu, D. F. Wong - 1999
42 Optimal Wiresizing for Interconnects with Multiple Sources – Jason Cong, Lei He - 1996
66 Interconnect design for deep submicron ICs – Jason Cong, Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo - 1997
25 Interconnect Delay Estimation Models for Synthesis and Design Planning – Jason Cong, et al. - 1999
16 An Efficient Approach To Simultaneous Transistor And Interconnect Sizing – Jason Cong, Lei He - 1996
11 Greedy wire-sizing is linear time – Chris C. N. Chu, Martin D. F. Wong - 1998
11 An efficient and optimal algorithm for simultaneous buffer and wire sizing – Chris C. N. Chu, D. F. Wong - 1999
Synthesis of clock and power/ground networks – Cheng-kok Koh, Jitesh Jain, Stephen F. Cauley