Bit-Level Analysis of an SRT Divider Circuit (1995)

by Randal E. Bryant
Venue:IN PROCEEDINGS OF THE 33RD DESIGN AUTOMATION CONFERENCE, PAGES 661--665, LAS VEGAS, NV
Citations:24 - 0 self

Active Bibliography

Bit-Level Analysis of an SRT Divider Circuit – unknown authors
894 Symbolic Boolean manipulation with ordered binary-decision diagrams – Randal E Bryant - 1992
2474 Compositional Model Checking – E. M. Clarke, D. E. Long, K. L. Mcmillan - 1999
587 Symbolic Model Checking: 10^20 States and Beyond – J. R. Burch, E. M. Clarke, K. L. McMillan, D. L. Dill, L. J. Hwang - 1992
620 Counterexample-guided Abstraction Refinement – Edmund Clarke, Orna Grumberg, Somesh Jha, Yuan Lu, Helmut Veith - 2000
23 Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking – Yirng-an Chen, Edmund Clarke, Pei-Hsin Ho, Yatin Hoskote, Timothy Kam, Manpreet Khaira, John O'Leary, Xudong Zhao - 1996
376 Model Checking for Programming Languages using VeriSoft – Patrice Godefroid - 1997
4 Ordered Binary Decision Diagrams and Their Significance in Computer-Aided Design of VLSI Circuits -- a Survey – Christoph Meinel , Thorsten Theobald - 1998
297 Reachability Analysis of Pushdown Automata: Application to Model-Checking – Ahmed Bouajjani, Javier Esparza, Oded Maler - 1997