3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration (2001)

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by Kaustav Banerjee , Shukri J. Souri , Pawan Kapur , Krishna C. Saraswat
Venue:Proceedings of the IEEE
Citations:98 - 6 self

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On Threshold Circuits and Analysis of . . . – Shamik Das - 2004
Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications – Shukri Souri Kaustav, Kaustav Banerjee, Amit Mehrotra - 2000
17 Multiple Si layer ICs: motivation, performance analysis, and design implications – Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna C. Saraswat - 2000
REAL TIME IMAGE PROCESSING ON PARALLEL ARRAYS FOR GIGASCALE INTEGRATION – Meng Chai, Sek Meng Chai, David E. Schimmel, Linda M. Wills - 1999
7 Heterogeneous Architecture Models for Interconnect-Motivated System Design – Sek Meng Chai, Tarek M. Taha, D. Scott Wills, Senior Member, James D. Meindl, Life Fellow - 2000
Global (Interconnect) Warning – K Banjeree - 2001
4 Coupled analysis of electromigration reliability and performance – Kaustav Banerjee, Amit Mehrotra - 2001
83 Rationale and challenges for optical interconnects to electronic chips – David A. B. Miller - 2000
12 Requirements for Models of Achievable Routing – Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt - 2000
19 The scaling challenge: Can correct-by-construction design help – Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond A. Kirkpatrick - 2003
10 Limitations and Challenges of Computer-Aided Design Technology for CMOS VLSI – Randal E. Bryant, Kwang-Ting Cheng, Andrew B. Kahng, Kurt Keutzer, Wojciech Maly, Richard Newton - 2001
395 The Future of Wires – Mark Horowitz, Ron Ho, Ken Mai - 1999
5 Wiring layer assignments with consistent stage delays – Andrew B. Kahng, Dirk Stroobandt - 2000
7 Toward Accurate Models of Achievable Routing – Andrew B. Kahng, Stefanus Mantik, Dirk Stroobandt - 2001
Routing issues in Nanometer-scale . . . – Tianpei Zhang - 2006
5 Analysis and Optimization of Thermal Issues in High-Performance VLSI – Kaustav Banerjee, Massoud Pedram, Amir H. Ajami - 2001
Non-Uniform Interconnect Temperature-Driven Buffer Insertion – Amir H. Ajami, Kaustav Banerjee, Massoud Pedram
48 A Methodology for Correct-by-Construction Latency Insensitive Design – Luca P. Carloni, Kenneth L. McMillan , Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli - 2003
25 Interconnect Estimation and Planning for Deep Submicron Designs – Jason Cong, David Zhigang Pan - 1998