Low-cost Protection for SER Upsets and Silicon Defects

by Mojtaba Mehrara , Mona Attariyan , Smitha Shyam , Kypros Constantinides , Valeria Bertacco , Todd Austin
Citations:2 - 1 self

Documents Related by Co-Citation

2 Self-calibrating Networks-on-Chip – Frédéric Worm, Patrick Thiran, Giovanni De Micheli, Paolo Ienne - 2005
3 DRAIN: Distributed Recovery Architecture for Inaccessible Nodes in Multi-core Chips – Andrew Deorio, Kostantinos Aisopos, Valeria Bertacco, Li-shiuan Peh
1 Adapteva Epiphany multi core architecture – Adapteva
1 Online NoC switch fault detection and diagnosis using a high level fault model – M Sedghi N, Z Navabi - 2007
1 Error-locality-aware linear coding to protect multi-bit upset in srams – S Shamshiri, K-T Cheng - 2010
3 ARIADNE: Agnostic Reconfiguration In A Disconnected Network Environment – Konstantinos Aisopos, Andrew Deorio, Li-shiuan Peh, Valeria Bertacco
3 End-to-end error correction and online diagnosis for on-chip networks – S SHAMSHIRI, A GHOFRANI, K-T CHENG - 2011
4 ApplicationAware Diagnosis of Runtime Hardware Faults – Extremetechnologyscalinginsilicondevicesdrasticallyaffectsreliability Particularlybecauseofruntimefa, Andrea Pellegrini, Valeria Bertacco
5 Next generation on-chip networks: What kind of congestion control do we need – G Nychis, C Fallin, T Moscibroda, O Mutlu - 2009
26 Ultra low-cost defect protection for microprocessor pipelines – Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin - 2006
10 Vicis: A reliable network for unreliable silicon – D Fick, A DeOrio, J Hu, V Bertacco, D Blaauw, D Sylvester - 2009
27 BulletProof: A Defect-Tolerant CMP Switch Architecture – Kypros Constantinides, Stephen Plaza, Jason Blome, Bin Zhang, Valeria Bertacco, Scott Mahlke, Todd Austin, Michael Orshansky - 2006
4 Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and – A P Frantz, F L Kastensmidt, L Carro, E F Cota - 2006
92 Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline – Nicholas J. Wang, Justin Quek, Todd M. Rafacz, Sanjay J. Patel - 2004
400 B.: “Principles and Practices of Interconnection Networks – W J Dally, Towles - 2003
297 Design challenges of technology scaling – S Borkar - 1999
283 Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures – Vikas Agarwal, M.S. Hrishikesh, Stephen W. Keckler, Doug Burger - 2000
54 Networks on chip: a new paradigm for systems on chip design – Luca Benini - 2002
282 The PARSEC benchmark suite: Characterization and architectural implications – Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, Kai Li - 2008