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57
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2605
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17
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Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
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48
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42
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Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation
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793
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Symbolic Boolean manipulation with ordered binary-decision diagrams
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6
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464
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Symbolic Model Checking: An Approach to the State Explosion Problem
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12
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Comparing Layouts with HDL Models: A Formal Verification Technique
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9
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Modeling of Circuit Delays
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22
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Formal Verification of Digital Circuits Using Symbolic Ternary System Models
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51
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Private Communication
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19
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A.: Verifying pipelined hardware using symbolic logic simulation
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4
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Mapping switch-level simulation onto gate-level hardware accelerators," 28th DAC
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3
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Timing Analysis in Precharge/Unate Networks
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6
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Self resetting logic register and incrementer
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26
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Certified Timing Verification and the Transition Delay of a Logic Circuit
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17
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Static Timing Analysis For Self Resetting Circuits
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17
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