Built-In Self-Test for Signal Integrity (2001)

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by Mehrdad Nourani , Amir Attarha
Citations:11 - 2 self

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7 Signal Integrity: Fault Modeling and Testing in High-Speed SoCs – Mehrdad Nourani, Amir Attarha
2 Detecting Signal-Overshoots for Reliability Analysis in High-Speed System-on-Chips – Mehrdad Nourani, Amir R. Attarha - 2002
Digital Circuit Signal Integrity Enhancement by Monitoring Power Grid Activity 1 – J. Semião, M. Rodriguez-irago, L. Piccoli, F. Vargas, M. B. Santos, I. C. Teixeira, J. J. Rodríguez Andina, J. P. Teixeira
Mixed-signal Design of Dynamic Delay Buffers to Improve Tolerance to Power Supply and Temperature Variations – J. Semião, J. Freijedo, J. J. Rodríguez-andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations – J. Semião, J. J. Rodríguez-andina, F. Vargas, M. B. Santos, I. C. Teixeira, J. P. Teixeira
12 Test Pattern Generation for Signal Integrity Faults on Long Interconnects – Amir Attarha, Mehrdad Nourani - 2002
Power-Time Tradeoff in Test Scheduling for SoCs – Mehrdad Nourani And - 2003
Fault-Coverage Analysis Techniques of Crosstalk – In Chip Interconnects, Yi Zhao, Student Member, Sujit Dey - 2000
2 Signal Integrity Fault Analysis Using Reduced-Order Modeling – Amir Attarha, Mehrdad Nourani - 2002
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity – Tehranipour Ahmed Nourani - 2003
2 High-level Crosstalk Defect Simulation for System-on-Chip Interconnects – Xiaoliang Bai, Sujit Dey - 2001
6 Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture – Mohammad H. Tehranipour, Nisar Ahmed, Mehrdad Nourani - 2003
8 Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores – Xiaoliang Bai, Sujit Dey, Li Chen, Li Chen - 2001
Test Access Mechanism for Core Based System-on-Chip – M. Nourani, C. Papachristou
4 Time Domain Multiplexed TAM: Implementation and Comparison – Zahra Sadat Ebadi, Andre Ivanov - 2003
24 An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing – Mehrdad Nourani, Christos Papachristou - 2000
Test Planning and Design Space Exploration in a Core-based Environment – Erika Cota Luigi - 2002
1 Addressing Useless Test Data in Core-Based System-on-a-Chip Test – Paul T. Gonciari, Bashir M. Al-hashimi, Nicola Nicolici, Paul T. Gonciari, Bashir M. Al-hashimi, Nicola Nicolici
Efficiency of Adiabatic Logic for Low-Power, Low-Noise VLSI – Hamid Mahmoodi-Meimand, Ali Afzali-kusha