Built-In Self-Test for Signal Integrity (2001)

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by Mehrdad Nourani , Amir Attarha
Citations:11 - 2 self

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7 Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Digital Circuit Signal Integrity Enhancement by Monitoring Power Grid Activity 1
2 Detecting Signal-Overshoots for Reliability Analysis in High-Speed System-on-Chips – - 2002
Mixed-signal Design of Dynamic Delay Buffers to Improve Tolerance to Power Supply and Temperature Variations
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations
13 Test Pattern Generation for Signal Integrity Faults on Long Interconnects – - 2002
Power-Time Tradeoff in Test Scheduling for SoCs – - 2003
Fault-Coverage Analysis Techniques of Crosstalk – - 2000
Test Access Mechanism for Core Based System-on-Chip
25 An ILP Formulation to Optimize Test Access Mechanism in System-on-Chip Testing – - 2000
2 Signal Integrity Fault Analysis Using Reduced-Order Modeling – - 2002
9 Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores – - 2001
Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity – - 2003
2 High-level Crosstalk Defect Simulation for System-on-Chip Interconnects – - 2001
8 Testing SoC Interconnects for Signal Integrity Using Extended JTAG Architecture – - 2003
Test Planning and Design Space Exploration in a Core-based Environment – - 2002
5 An Efficient Model for Frequency-Dependent On-Chip Inductance – - 2001
4 Time Domain Multiplexed TAM: Implementation and Comparison – - 2003
2 Addressing Useless Test Data in Core-Based System-on-a-Chip Test