Power-Delay Optimizations in Gate Sizing (2000)

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by Sachin S. Sapatnekar , Weitong Chuang
Citations:8 - 0 self

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9 Power vs. Delay in Gate Sizing: Conflicting Objectives? – Sachin S. Sapatnekar, Weitong Chuang - 1995
8 Process-variation-resistant dynamic power . . . – Fei Hu - 2006
5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
104 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
1041 Wattch: A Framework for Architectural-Level Power Analysis and Optimizations – David Brooks, Vivek Tiwari, Margaret Martonosi - 2000
3183 A computational approach to edge detection – John Canny - 1986
1332 A training algorithm for optimal margin classifiers – Bernhard E. Boser, et al. - 1992
228 A Survey of Power Estimation Techniques in VLSI Circuits – Farid N. Najm - 1994
434 Low-Power CMOS Digital Design – Anantha P. Chandrakasan, Samuel Sheng, Robert W. Brodersen - 1992