Optimization of Phase-Locked Loop Circuits via Geometric Programming (2003)

by David M. Colleran , Clemenz Portmann , Arash Hassibi , Cesar Crusius , Sunderarajan S. Mohan , Stephen Boyd , Thomas H. Lee , Maria del Mar Hershenson
Venue:In Proceedings of the Custom Integrated Circuits Conference (CICC
Citations:9 - 3 self

Active Bibliography

16 Optimal Power Control in Interference Limited Fading Wireless Channels with Outage Probability Specifications – Sunil Kandukuri, Stephen Boyd - 2000
7 Optimal allocation of local feedback in multistage amplifiers via geometric programming – Joel L. Dawson, Stephen P. Boyd, Maria Del Mar Hershenson, Thomas H. Lee - 2001
7 Design and optimization of LC oscillators – Maria del Mar Hershenson, Ali Hajimiri, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee - 1999
25 Optimization of inductor circuits via geometric programming – Maria Del Mar Hershenson, Sunderarajan S. Mohan, Stephen P. Boyd, Thomas H. Lee - 1999
51 Optimal design of a CMOS op-amp via geometric programming – Maria Del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee - 2001
6 Virtual damping and Einstein relation in oscillators – Donhee Ham, Ali Hajimiri - 2003
Joint Design-Time and Post-Silicon Optimization for Digitally Tuned Analog Circuits – Wei Yao, Yiyu Shi, Lei He, Sudhakar Pamarti
27 Digital Circuit Optimization via Geometric Programming – Stephen P. Boyd, Seung-jean Kim, Dinesh D. Patil, Mark A. Horowitz - 2005
permission. Power-Performance Tradeoffs In ASICs for Next Generation Wireless Communication Datapaths – Farhana Sheikh, Farhana Sheikh, Farhana Sheikh
Conic Geometric Programming – Venkat Ch, Rasekaranc W, Parikshit Shah - 2013
1 An Optimal Power Allocation Scheme for the STC Hybrid–ARQ over Energy Limited Networks – Hongbo Liu, Leonid Razoumov, Narayan M, Predrag Spasojević
2 Global injectivity and multiple equilibria in uni- and bi-molecular reaction networks – Casian Pantea, Gheorghe Craciun - 2012
Outline . – Clock-Recovery Phase-Alignment Approaches, Oversampled Crcs, D Out, D In
6 Integrated Regulation for Energy-Efficient Digital Circuits – Elad Alon, Mark Horowitz
97 Supply and threshold voltage scaling for low power CMOS – Ricardo Gonzalez, Benjamin M. Gordon, Mark A. Horowitz - 1997
A MIXED PLL/DLL ARCHITECTURE FOR LOW JITTER CLOCK GENERATION – unknown authors
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS 1 Discrete-Time, Linear Periodically Time-Variant – Socrates D. Vamvakos, Vladimir Stojanović, Borivoje Nikolić, Senior Member
4 Replica compensated linear regulators for supply-regulated phase-locked loops – Elad Alon, Student Member, Jaeha Kim, Sudhakar Pamarti, Ken Chang, Mark Horowitz - 2006
1 Optimal design of CMOS low noise amplifiers via geometric programming – Cong Liu, Yinghua Li - 2001