Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization (1995)

by Harsha Sathyamurthy , Sachin S. Sapatnekar , John P. Fishburn
Venue:Proc. Int'l Conf. on Computer-Aided Design
Citations:12 - 0 self

Document Versions

Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization –Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn — 1995 — Proc. Int'l Conf. on Computer-Aided Design
Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization –Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn — 1995 — Proc. Int'l Conf. on Computer-Aided Design