Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization (1995)

by Harsha Sathyamurthy , Sachin S. Sapatnekar , John P. Fishburn
Venue:Proc. Int'l Conf. on Computer-Aided Design
Citations:12 - 0 self

Active Bibliography

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58 Clock Distribution Networks in Synchronous Digital Integrated Circuits – Eby G. Friedman - 2001
15 Optimizing dominant time constant in RC circuits – Lieven Vandenberghe, Stephen Boyd, Abbas El Gamal - 1996
8 Power-Delay Optimizations in Gate Sizing – Sachin S. Sapatnekar, Weitong Chuang - 2000
Novel Modeling and Optimization Techniques for Nano-Scale VLSI Designs – Sanghamitra Roy - 2008
246 An enhanced access and cycle time model for on-chip caches – Steven J. E. Wilton - 1994
243 An adaptive, nonuniform cache structure for wire-delay dominated on-chip caches – Changkyu Kim, Doug Burger, Stephen W. Keckler - 2002
54 Optimal design of a CMOS op-amp via geometric programming – Maria Del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee - 2001
a Novel Clock Network – Vadim Gutnik, Anantha Chandrakasan, Vadim Gutnik - 2000