Speeding up Pipelined Circuits through a Combination of Gate Sizing and Clock Skew Optimization (1995)

by Harsha Sathyamurthy , Sachin S. Sapatnekar , John P. Fishburn
Venue:Proc. Int'l Conf. on Computer-Aided Design
Citations:12 - 0 self

Active Bibliography

103 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
56 Clock Distribution Networks in Synchronous Digital Integrated Circuits – Eby G. Friedman - 2001
16 Optimizing dominant time constant in RC circuits – Lieven Vandenberghe, Stephen Boyd, Abbas El Gamal - 1996
8 Power-Delay Optimizations in Gate Sizing – Sachin S. Sapatnekar, Weitong Chuang - 2000
Novel Modeling and Optimization Techniques for Nano-Scale VLSI Designs – Sanghamitra Roy - 2008
16 A Fresh Look at Retiming via Clock Skew Optimization – Rahul B. Deokar, Sachin S. Sapatnekar - 1995
12 Interleaving buffer insertion and transistor sizing into a single optimization – Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim - 1998
1 Macro-Driven Circuit Design Methodology for High-Performance Datapaths – Mahadevamurty Nemani, Vivek Tiwari - 2000
51 Optimal design of a CMOS op-amp via geometric programming – Maria Del Mar Hershenson, Stephen P. Boyd, Thomas H. Lee - 2001
17 Timing and Area Optimization for Standard-Cell VLSI Circuit Design – Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj - 1995
Chip and Package Co-Design of Clock Networks – Qing Zhu, Wayne Wei-ming Dai, David Helmbold, Martine Schlag - 1995
Optimal Wire and Transistor Sizing for Circuits with Non-Tree Topology – Lieven V
28 Optimal Wire and Transistor Sizing for Circuits with Non-Tree Topology – Lieven Vandenberghe, Stephen Boyd, Abbas El Gamal - 1997
27 Digital Circuit Optimization via Geometric Programming – Stephen P. Boyd, Seung-jean Kim, Dinesh D. Patil, Mark A. Horowitz - 2005
7 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs – Jason Cong, Lei He - 1997
5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
2 Race-condition-aware clock skew scheduling – Shih-hsu Huang
6A-1 Clock Skew Scheduling with Delay Padding for Prescribed Skew Domains ∗ – Chuan Lin, Hai Zhou
27 Utilizing the Retiming-Skew Equivalence in a Practical Algorithm for Retiming Large Circuits – Sachin S. Sapatnekar, Rahul B. Deokar - 1996