Efficient and Accurate Gate Sizing with Piecewise Convex Delay Models (2005)

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by Hiran Tennakoon , Carl Sechen
Venue:DAC 2005
Citations:4 - 0 self

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Novel Modeling and Optimization Techniques for Nano-Scale VLSI Designs – Sanghamitra Roy - 2008
2 Numerically convex forms and their application in gate-sizing – Sanghamitra Roy, Weijen Chen, Charlie Chung-ping Chen, Yu Hen Hu - 2007
ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems – S. Roy, et al. - 2006
unknown title – Sanghamitra Roy
12 A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing – Seung-jean Kim, Stephen P. Boyd, Sunghee Yun, Dinesh D. Patil, Mark A. Horowitz - 2004
29 Digital Circuit Optimization via Geometric Programming – Stephen P. Boyd, Seung-jean Kim, Dinesh D. Patil, Mark A. Horowitz - 2005
2 Low Power Design Automation – David Graeme Chinnery - 2006
Freescale Semiconductor – Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma
1 Sensitivity-Guided Metaheuristics for Accurate Discrete Gate Sizing – Jin Hu, Andrew B. Kahng, Seokhyeong Kang, Myung-chul Kim, Igor L. Markov
7 Revisiting the Linear Programming Framework for Leakage Power vs. Performance Optimization – Kwangok Jeong, Andrew B. Kahng, Hailong Yao
6 An Efficient Method for Large-Scale Gate Sizing – Siddharth Joshi, Stephen Boyd
1 LARTTE: A Posynomial-Based Lagrangian Relaxation Tuning Tool for Fast and Effective Gate-Sizing and Multiple Vt Assignment – Hsinwei Chou, Yu-hao Wang, Charlie Chung-ping Chen
Noise Considerations in . . . – Chandu Visweswariah, Ruud A. Haring, Andrew R. Conn
8 Linear Programming for Sizing, Vth and Vdd Assignment – D. G. Chinnery, K. Keutzer - 2005
8 Power-Delay Optimizations in Gate Sizing – Sachin S. Sapatnekar, Weitong Chuang - 2000
5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
102 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
19 Uncertainty-Aware Circuit Optimization – Xiaoliang Bai, Chandu Visweswariah, Philip N. Strenski, David J. Hathaway - 2002
1 A Geometric Programming-based Worst-Case Gate Sizing Method Incorporating Spatial Correlation – Jaskirat Singh, Vidyasagar Nookala, Zhi-quan Luo, Sachin S. Sapatnekar