Digital Circuit Optimization via Geometric Programming (2005)

by Stephen P. Boyd , Seung-jean Kim , Dinesh D. Patil , Mark A. Horowitz
Venue:Operations Research
Citations:27 - 7 self

Active Bibliography

permission. Low Power Design Automation – David Graeme Chinnery, David Graeme Chinnery, David Graeme Chinnery
2 Low Power Design Automation – David Graeme Chinnery - 2006
5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
permission. Power-Performance Tradeoffs In ASICs for Next Generation Wireless Communication Datapaths – Farhana Sheikh, Farhana Sheikh, Farhana Sheikh
12 A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing – Seung-jean Kim, Stephen P. Boyd, Sunghee Yun, Dinesh D. Patil, Mark A. Horowitz - 2004
11 Area and Delay Trade-offs in the Circuit and Architecture . . . – Ian Kuon, Jonathan Rose - 2008
103 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
66 Interconnect design for deep submicron ICs – Jason Cong, Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo - 1997
6 An Efficient Method for Large-Scale Gate Sizing – Siddharth Joshi, Stephen Boyd
2 POWER EFFICIENT DESIGN OF SRAM ARRAYS AND OPTIMAL DESIGN OF SIGNAL AND POWER DISTRIBUTION NETWORKS IN VLSI CIRCUITS – Behnam Amelifard - 2007
1 A Heuristic Method for Statistical Digital Circuit Sizing – Stephen Boyd , Seung-Jean Kim , Dinesh Patil , Mark Horowitz
Novel Modeling and Optimization Techniques for Nano-Scale VLSI Designs – Sanghamitra Roy - 2008
2 Numerically convex forms and their application in gate-sizing – Sanghamitra Roy, Weijen Chen, Charlie Chung-ping Chen, Yu Hen Hu - 2007
7 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs – Jason Cong, Lei He - 1997
Optimal Wire and Transistor Sizing for Circuits with Non-Tree Topology – Lieven V
28 Optimal Wire and Transistor Sizing for Circuits with Non-Tree Topology – Lieven Vandenberghe, Stephen Boyd, Abbas El Gamal - 1997
7 An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation – I-min Liu, Adnan Aziz, D. F. Wong, Hai Zhou - 1999
2 Combined transistor sizing with buffer insertion for timing optimization – Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji, Juho Kim - 1998
16 Optimizing dominant time constant in RC circuits – Lieven Vandenberghe, Stephen Boyd, Abbas El Gamal - 1996