DAISY: Dynamic Compilation for 100% Architectural Compatibility (1997)

by Kemal Ebcioglu , Erik R. Altman
Citations:184 - 13 self

Active Bibliography

24 Dynamic binary translation and optimization – Kemal Ebcioglu, Erik Altman, Michael Gschwind, Sumedh Sathaye - 2000
3 Optimization of VLIW Compatibility Systems Employing Dynamic Rescheduling – Thomas M. Conte, Sumedh W. Sathaye
RC22025 (98128) 18 July 2000 Computer Science – Ibm Research Report, Kemal Ebcioglu, Erik Altman, Michael Gschwind, Sumedh Sathaye - 2001
2 Sathaye, \Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility – Thomas M. Conte, Sumedh W. Sathaye - 1997
115 The Multiscalar Architecture – Manoj Franklin - 1993
7 MPS: Miss path scheduling for multiple-issue processors – Sanjeev Banerjia, Sumedh W. Sathaye, Student Member, N. Menezes, Thomas M. Conte - 1998
Inherently Lower Complexity Architectures using Dynamic Optimization – Michael Gschwind, Erik Altman - 2002
9 Binary translation and architecture convergence issues for IBM System/390 – Michael Gschwind, Erik Altman, Sumedh Sathaye - 2000
4 A Persistent Rescheduled--Page Cache for low-overhead object-code compatibility in VLIW architectures – Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia - 1996
22 Execution-based scheduling for VLIW architectures – Kemal Ebcioglu, Erik R. Altman, Sumedh Sathaye, Michael Gschwind
TREEGION SCHEDULING FOR VLIW PROCESSORS – William Andrew Havaki, Jr. - 1997
21 Achieving High Levels of Instruction-Level Parallelism With Reduced Hardware Complexity – Michael S. Schlansker, B. Ramakrishna Rau, Scott Mahlke, Vinod Kathail, Richard Johnson, Sadun Anik, Santosh G. Abraham - 1997
18 Enhancing Instruction Level Parallelism Through Compiler-Controlled Speculation – Roger Alexander Bringmann - 1995
7 Modulo Scheduling for Control-Intensive General-Purpose Programs – Daniel Michael Lavery, Daniel Michael Lavery, Ph. D - 1997
39 Exploiting Instruction Level Parallelism in the Presence of Conditional Branches – Scott Alan Mahlke - 1996
68 Exploiting Instruction Level Parallelism in Processors by Caching Scheduled Groups – Ravi Nair, Ravi Nair, Martin E. Hopkins, Martin E. Hopkins - 1996
1 A co-designed virtual machine for instruction level distributed processing – Ho-seop Kim
40 A Trace Cache Microarchitecture and Evaluation – Eric Rotenberg - 1999
6 Trace Cache Design for Wide-Issue Superscalar Processors – Sanjay Jeram Patel, Sanjay Jeram Patel, Chair Yale, N. Patt - 1999