Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program (2003)

Cached

Download Links

by Tezaswi Raja , Vishwani D. Agrawal , Michael L. Bushnell
Venue:in Proc. of 16th International Conference on VLSI Design
Citations:17 - 10 self

Active Bibliography

7 CMOS Circuit Design for Minimum Dynamic Power and Highest Speed – Tezaswi Raja , Vishwani D. Agrawal , Michael L. Bushnell - 2004
4 Variable Input Delay CMOS Logic for Low Power Design – Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell - 2005
8 Process-variation-resistant dynamic power . . . – Fei Hu - 2006
A Generalized Minimum Dynamic Power and High-Speed Design Methods for . . . – n.n. - 2004
4 Design of variable input delay gates for low dynamic power circuits – Tezaswi Raja, Vishwani Agrawal, Michael Bushnell - 2005
332 Snopt: An SQP Algorithm For Large-Scale Constrained Optimization – Philip E. Gill, Walter Murray, Michael, Michael A. Saunders - 1997
Printed in the United States of America Transistor Sizing of Logic Gates to Maximize Input Delay Variability – Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell - 2005
2 Variable Input Delay CMOS Logic Design for Low Dynamic Power Circuits – Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell - 2005
GLITCH-FREE DESIGN OF LOW POWER ASICS USING CUSTOMIZED RESISTIVE – Feedthrough Cells, Michael L. Bushnell, Vishwani D. Agrawal