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103 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
109 Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model – John Lillis, Chung-kuan Cheng, Senior Member, Ting-ting Y. Lin - 1995
53 Optimal Wiresizing Under the Distributed Elmore Delay Model – Jason Cong, Kwok-shing Leung - 1993
365 The Transient Response of Damped Linear Networks with Particular Regard to Wideband Ampli ers – W C Elmore - 1948
42 Optimal Wiresizing for Interconnects with Multiple Sources – Jason Cong, Lei He - 1996
41 Challenges and Opportunities for Design Innovations in Nanometer Technologies – Jason Cong - 1997
73 Wire Segmenting for Improved Buffer Insertion – Charles Alpert, Anirudh Devgan - 1997
45 Closed form solution to simultaneous buffer insertion/sizing and wire sizing – Chris C. N. Chu, D. F. Wong - 1997
23 Global wires harmful – R Otten - 1998
50 Simulataneous Driver and Wire Sizing for Performance and Power Optimization – Jason Cong, Cheng-kok Koh - 1994
19 Simultaneous buffer and wire sizing for performance and power optimization – Jason Cong, Cheng-kok Koh, Kwok-shing Leung - 1996
28 Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation – C-P Chen, Y-W Chang, D F Wong - 1996
25 Interconnect Delay Estimation Models for Synthesis and Design Planning – Jason Cong, et al. - 1999
57 Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization – Takumi Okamoto , Jason Cong - 1996
79 Planning For Performance – Ralph H. J. M. Otten, Robert K. Brayton - 1998
67 Buffer Block Planning for Interconnect-Driven Floorplanning – Jason Cong, Tianming Kong, David Zhigang Pan - 1999
38 GLOBAL INTERCONNECT SIZING AND SPACING WITH CONSIDERATION OF COUPLING CAPACITANCE – Jason Cong, et al. - 1997
80 Ginneken, “Buffer Placement in Distributed RCtree Networks for Minimal Elmore Delay – L P P van - 1990
67 Automatic Floorplan Design – R H J M Otten - 1982