Active Bibliography

103 Performance optimization of VLSI interconnect layout – Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden - 1996
1 Modeling and Layout Optimization of VLSI Devices and Interconnects in Deep Submicron Design – Jason Cong - 1997
5 Modeling and Optimization of VLSI Interconnects – Lei He - 1999
69 An Interconnect-Centric Design Flow for Nanometer Technologies – Jason Cong - 1999
22 Interconnect Performance Estimation Models for Design Planning – Jason Cong, Zhigang (David) Pan - 2001
42 Optimal Wiresizing for Interconnects with Multiple Sources – Jason Cong, Lei He - 1996
12 Performance Driven Global Routing for Standard Cell Design – Jason Cong, Patrick H. Madden - 1997
8 Interconnect Performance Estimation Models for Synthesis and Design Planning – Jason Cong , Zhigang Pan
Timing-Driven Interconnect Synthesis ∗ – Jiang Hu, Gabriel Robins, C. N. Sze
7 An Efficient Technique for Device and Interconnect Optimization in Deep Submicron Designs – Jason Cong, Lei He - 1997
25 Interconnect Layout Optimization under Higher-Order RLC Model for MCM Designs – Jason Cong, Cheng-Kok Koh, Patrick H. Madden - 1997
38 GLOBAL INTERCONNECT SIZING AND SPACING WITH CONSIDERATION OF COUPLING CAPACITANCE – Jason Cong, et al. - 1997
7 Theory and Algorithm of Local-Refinement-Based Optimization with Application to Device and Interconnect Sizing – Jason Cong, Lei He - 1999
19 Buffered Steiner trees for difficult instances – C. J. Alpert, M. Hrkic, J. Hu, A. B. Kahng, J. Lillis, B. Liu - 2002
9 A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing – Chris C. N. Chu, D. F. Wong - 1999
10 Timing optimization for multisource nets: characterization and optimal repeater insertion – John Lillis, Chung-Kuan Cheng - 1999
57 Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization – Takumi Okamoto , Jason Cong - 1996
6 Algorithms for Performance Driven Design of Integrated Circuits – John Patrick Lillis, John Patrick Lillis - 1996
10 Spec-based Repeater Insertion and Wire Sizing for On-chip Interconnect – Noel Menezes, Chung-Ping Chen - 1999