Uncertainty-Aware Circuit Optimization (2002)

Cached

Download Links

by Xiaoliang Bai , Chandu Visweswariah , Philip N. Strenski , David J. Hathaway
Venue:IN DAC
Citations:17 - 1 self

Documents Related by Co-Citation

136 Statistical timing analysis considering spatial correlations using a single PERT-like traversal – Hongliang Chang, Sachin S - 2003
86 Statistical timing analysis for intra-die process variations with spatial correlations – A Agarwal, D Blaauw, V Zolotov - 2003
147 TILOS: A Posynomial Programming Approach to Transistor Sizing – J P Fishburn, A E Dunlop - 1985
39 Statistical timing analysis using bounds and selective enumeration – A Agarwal, V Zolotov, D T Blaauw - 2003
69 Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation – Chung-ping Chen, Chris C. N. Chu, D. F. Wong - 1997
81 An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization – Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-mo Kang - 1993
37 Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits – J. A. G. Jess, K. Kalafala, S. R. Naidu, R. H. J. M. Otten, C. Visweswariah - 2003
133 Logical effort: designing fast CMOS circuits – I Sutherland, B Sproull, D Harris - 1999
31 Fast statistical timing analysis by probabilistic event propagation – Jing-jia Liou, Kwang-ting Cheng, Ip Kundu, Angela Krstić - 2001
95 First-order incremental block-based statistical timing analysis – C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan - 2004
85 The greatest of a finite set of random variables – C Clark - 1961
60 A General Probabilistic Framework for Worst Case Timing Analysis – Michael Orshansky, Kurt Keutzer - 2002
1243 Numerical Optimization – J Nocedal, S J Wright - 2000
13 JiffyTune: Circuit optimization using time-domain sensitivities – A R Conn, P K Coulman, R A Haring, G L Morill, C Visweswariah, C W Wu - 1998
18 Statistical optimization of leakage power considering process variations using dual-vth and sizing – Ashish Srivastava, Dennis Sylvester, David Blaauw - 2004
18 Gate sizing using lagrangian relaxation combined with a fast gradient-based pre-processing step – H Tennakoon, C Sechen - 2002
27 E.T.A.F.: Gate Sizing Using a Statistical Delay Model – M Berkelaar, Jacobs - 2000
22 A New Class of Convex Functions for Delay Modeling and their Application to the Transistor Sizing Problem”, in – K Kasamsetty, M Ketkar, S S Sapatnekar - 2002
57 Block-based static timing analysis with uncertainty – A Devgan, C V Kashyap - 2003