Machine-description driven compilers for EPIC and VLIW processors. Design Automation for Embedded Systems (1999)

by B. Ramakrishna Rau , Vinod Kathail , Shail Aditya
Citations:16 - 7 self

Active Bibliography

281 Iterative modulo scheduling: An algorithm for software pipelining loops – B. Ramakrishna Rau - 1994
13 Reducing The Impact Of Register Pressure On Software Pipelined Loops – Josep Llosa, Margarita Espuny - 1996
84 Iterative Modulo Scheduling – B. Ramakrishna Rau - 1995
21 Achieving High Levels of Instruction-Level Parallelism With Reduced Hardware Complexity – Michael S. Schlansker, B. Ramakrishna Rau, Scott Mahlke, Vinod Kathail, Richard Johnson, Sadun Anik, Santosh G. Abraham - 1997
171 Instruction-Level Parallel Processing: History, Overview and Perspective – B. Ramakrishna Rau, Joseph A. Fisher - 1992
31 Distributed Modulo Scheduling – Marcio Merino Fernandes, Josep Llosa, Nigel Topham - 1999
115 The Multiscalar Architecture – Manoj Franklin - 1993
25 Modulo Scheduling With Isomorphic Control Transformations – Nancy Jeanne Warter - 1994
17 Elcor’s Machine Description System: Version 3.0 – Shail Aditya, Vinod Kathail, B. Ramakrishna Rau - 1998
131 Lifetime-Sensitive Modulo Scheduling – Richard A. Huff - 1993
11 Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures – Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero - 2001
1 Backtracking-based Instruction Scheduling To Fill Branch Delay Slots – Ivan D. Baev, Waleed M. Meleis, Santosh G. Abraham
5 A Systematic Approach to Delivering INSTRUCTION-LEVEL PARALLELISM IN EPIC SYSTEMS – John Wollenburg Sias - 2005
9 Efficient Backtracking Instruction Schedulers – Santosh G. Abraham - 2000
2 Global Instruction Scheduling for Multi-Threaded Architectures – Guilherme De Lima Ottoni - 2008
31 Height Reduction of Control Recurrences for ILP Processors – Michael Schlansker , Vinod Kathail, Sadun Anik - 1994
39 Exploiting Instruction Level Parallelism in the Presence of Conditional Branches – Scott Alan Mahlke - 1996
13 Lifetime-sensitive Modulo Scheduling in a Production Environment – Josep Llosa, Eduard Ayguade, Antonio Gonzalez, Mateo Valero, Jason Eckhardt
Advanced Pipelining and Instruction-Level Parallelism – n.n.