Machine-description driven compilers for EPIC and VLIW processors. Design Automation for Embedded Systems (1999)

by B. Ramakrishna Rau , Vinod Kathail , Shail Aditya
Citations:16 - 7 self

Active Bibliography

REDUCING THE IMPACT OF REGISTER PRESSURE ON SOFTWARE PIPELINED LOOPS – Advisor Mateo Valero - 1996
284 Iterative modulo scheduling: An algorithm for software pipelining loops – B. Ramakrishna Rau - 1994
84 Iterative Modulo Scheduling – B. Ramakrishna Rau - 1995
13 Reducing The Impact Of Register Pressure On Software Pipelined Loops – Josep Llosa, Margarita Espuny - 1996
unknown title – unknown authors
171 Instruction-Level Parallel Processing: History, Overview and Perspective – B. Ramakrishna Rau, Joseph A. Fisher - 1992
Modulo Scheduling, Machine Representations, and Register-Sensitive Algorithms – Dr. Santosh, Professor Edward, S. Davidson, John R. Birge, Alexandre Edouard Eichenberger, Alexandre Edouard Eichenberger, Co-chairs Santosh, G. Abraham, G. Abraham, Edward S. Davidson - 1997
21 Achieving High Levels of Instruction-Level Parallelism With Reduced Hardware Complexity – Michael S. Schlansker, B. Ramakrishna Rau, Scott Mahlke, Vinod Kathail, Richard Johnson, Sadun Anik, Santosh G. Abraham - 1997
117 The Multiscalar Architecture – Manoj Franklin - 1993