Design of Embedded Systems: Formal Models, Validation, and Synthesis (1999)

by S. Edwards , L. Lavagno , E. A. Lee , A. Sangiovanni-Vincentelli
Venue:PROCEEDINGS OF THE IEEE
Citations:106 - 9 self

Document Versions

Design of Embedded Systems: Formal Models, Validation, and Synthesis –S. Edwards, L. Lavagno, E. A. Lee, A. Sangiovanni-Vincentelli — 1999 — PROCEEDINGS OF THE IEEE
Design of Embedded Systems: Formal Models, Validation, and Synthesis –Stephen Edwards, Luciano Lavagno, Edward A. Lee, Alberto Sangiovanni–vincentelli — 1997 — Proceedings of the IEEE
Design of Embedded Systems: Formal Models, Validation, and Synthesis –Stephen Edwards, Luciano Lavagno, Edward A. Lee, Alberto Sangiovanni-Vincentelli — 1997 — Proceedings of the IEEE
Design of Embedded Systems: Formal Models, Validation, and Synthesis –Stephen A. Edwards, Luciano Lavagno, Edward A. Lee, L. Lavagno, E. A. Lee, Alberto Sangiovanni-Vincentelli — 1997 — Proceedings of the IEEE
Design of Embedded Systems: Formal Models, Validation, and Synthesis –Stephen Edwards, L. Lavagno, E. A. Lee, Alberto Sangiovanni-Vincentelli, Stephen Edwards, Luciano Lavagno, Edward A. Lee, Alberto Sangiovanni-vincentelli — 1997
Design of Embedded Systems: Formal Models, Validation, and Synthesis –Stephen Edwards, Luciano Lavagno, Edward A. Lee, Alberto Sangiovanni-vincentelli — 1997 — Proceedings of the IEEE