Gate Sizing Using Incremental Parameterized Statistical Timing Analysis (2005)

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by M. R. Guthaus , N. Venkateswaran , C. Visweswariah , V. Zolotov
Venue:In ICCAD
Citations:28 - 1 self

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1 On the Futility of Statistical Power Optimization – Jason Cong, Puneet Gupta, John Lee
Analysis and Optimization under Crosstalk and Variability in Deep Sub-Micron VLSI Circuits – Debjit Sinha - 2006
By – Hongliang Chang, C Hongliang Chang - 2006
1 Defining statistical timing sensitivity for logic circuits with large-scale process and environmental variations – Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi - 2008
12 A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing – Seung-jean Kim, Stephen P. Boyd, Sunghee Yun, Dinesh D. Patil, Mark A. Horowitz - 2004
3 Optimization objectives and models of variation for statistical gate sizing – Matthew R. Guthaus, Natesan Venkateswaran, Dennis Sylvester - 2005
20 Defining statistical sensitivity for timing optimization of logic circuits with largescale process and environmental variations,” Docket MC06172004P, Filed with the US Patent Office – Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi - 2005
8 Process-variation-resistant dynamic power . . . – Fei Hu - 2006
131 First-order incremental block-based statistical timing analysis – C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan - 2004