Gate Sizing Using Incremental Parameterized Statistical Timing Analysis (2005)

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by M. R. Guthaus , N. Venkateswaran , C. Visweswariah , V. Zolotov
Venue:In ICCAD
Citations:25 - 1 self

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1 On the Futility of Statistical Power Optimization – Jason Cong, Puneet Gupta John Lee
Analysis and Optimization under Crosstalk and Variability in Deep Sub-Micron VLSI Circuits – Debjit Sinha - 2006
3 Optimization objectives and models of variation for statistical gate sizing – Matthew R. Guthaus, Natesan Venkateswaran, Dennis Sylvester - 2005
12 A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing – Seung-jean Kim, Stephen P. Boyd, Sunghee Yun, Dinesh D. Patil, Mark A. Horowitz - 2004
20 Defining statistical sensitivity for timing optimization of logic circuits with largescale process and environmental variations,” Docket MC06172004P, Filed with the US Patent Office – Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi - 2005
New Block-Based Statistical Timing Analysis Approaches Without Moment Matching – Ruiming Chen, Hai Zhou
3 Probabilistic Dual-Vth Leakage Optimization under Variability – Azadeh Davoodi, Ankur Srivastava - 2005
38 An Efficient Algorithm for Statistical Minimization of Total Power under Timing Yield Constraints – Murari Mani, Anirudh Devgan, Michael Orshansky - 2005
Set of Gaussian Random Variables – Debjit Sinha, Hai Zhou, Senior Member, Narendra V. Shenoy, Senior Member
3 Improving the process-variation tolerance of digital circuits using gate sizing and statistical techniques – Osama Neiroukh, Xiaoyu Song - 2005
1 A Geometric Programming-based Worst-Case Gate Sizing Method Incorporating Spatial Correlation – Jaskirat Singh, Vidyasagar Nookala, Zhi-quan Luo, Sachin S. Sapatnekar
21.1 First-Order Incremental Block-Based Statistical Timing Analysis – C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan
128 First-order incremental block-based statistical timing analysis – C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan - 2004
BY – Qunzeng Liu - 2010
28 A General Framework for Accurate Statistical Timing Analysis Considering Correlations – Vishal Khandelwal, Ankur Srivastava - 2005
42 Statistical Timing Analysis Under Spatial Correlations – Hongliang Chang, Sachin S. Sapatnekar - 2005
Michael OrshanskyStatistical Characterization For Timing Sign-Off: From Silicon to – Savithri Sundareswaran, Jacob A. Abraham, David Blaauw, David Pan, Robert Flake, Back To Silicon
29 Digital Circuit Optimization via Geometric Programming – Stephen P. Boyd, Seung-jean Kim, Dinesh D. Patil, Mark A. Horowitz - 2005
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models – Khaled R. Heloue, Student Member, Farid N. Najm