Closing the Gap Between ASIC and Custom: An ASIC Perspective (2000)

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by D. G. Chinnery , K. Keutzer
Venue:DAC 2000
Citations:29 - 0 self

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permission. Low Power Design Automation – David Graeme Chinnery, David Graeme Chinnery, David Graeme Chinnery
2 Low Power Design Automation – David Graeme Chinnery - 2006
2 Timing-driven Partitioning and Timing Optimization of Mixed Static-Domino Implementations – Min Zhao - 2000
Analysis and Optimization Problems in High Speed . . . – Min Zhao - 1999
23 Skew-Tolerant Circuit Design – David Harris - 1999
2 Timing-driven Partitioning for Two-Phase Domino and Mixed Static/Domino Implementations – Min Zhao, Sachin S. Sapatnekar - 1999
17 Statistical Clock Skew Modeling with Data Delay Variations – David Harris, Sam Naffziger - 2001
10 Gate-Size Selection for Standard Cell Libraries – Frederik Beeftink, Prabhakar Kudva, David Kung, Leon Stok - 1998
Monotonic Static CMOS and Dual V T Technology – Tyler Thorp, Gin Yee, Carl Sechen
1 Technology Mapping Algorithms for Domino Logic – Min Zhao, Sachin S. Sapatnekar - 2002
27.1 Achieving 550 MHz in an ASIC Methodology – D. G. Chinnery, B. Nikolic, K. Keutzer
3 Achieving 550 MHz in an ASIC Methodology – D. G. Chinnery, B. Nikoli, K. Keutzer
8 Clocking and Clocked Storage Elements in a Multi-Gigahertz Environment – V. G. Oklobdzija - 2003
Power Minimization by Simultaneous Dual-V Assignment and Gate-sizing – Liqiong Wei, Kaushik Roy, Cheng-Kok Koh - 2000
Novel Modeling and Optimization Techniques for Nano-Scale VLSI Designs – Sanghamitra Roy - 2008
Freescale Semiconductor – Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma
7 An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation – I-min Liu, Adnan Aziz, D. F. Wong, Hai Zhou - 1999
4 Efficient and Accurate Gate Sizing with Piecewise Convex Delay Models – Hiran Tennakoon, Carl Sechen - 2005
2 Numerically convex forms and their application in gate-sizing – Sanghamitra Roy, Weijen Chen, Charlie Chung-ping Chen, Yu Hen Hu - 2007