|
2
|
Low Power Design Automation
– David Graeme Chinnery
- 2006
|
|
2
|
Timing-driven Partitioning and Timing Optimization of Mixed Static-Domino Implementations
– Min Zhao
- 2000
|
|
|
Analysis and Optimization Problems in High Speed . . .
– Min Zhao
- 1999
|
|
23
|
Skew-Tolerant Circuit Design
– David Harris
- 1999
|
|
2
|
Timing-driven Partitioning for Two-Phase Domino and Mixed Static/Domino Implementations
– Min Zhao, Sachin S. Sapatnekar
- 1999
|
|
12
|
Statistical Clock Skew Modeling with Data Delay Variations
– David Harris, Sam Naffziger
- 2001
|
|
7
|
Gate-Size Selection for Standard Cell Libraries
– Frederik Beeftink, Prabhakar Kudva, David Kung, Leon Stok
- 1998
|
|
1
|
Technology Mapping Algorithms for Domino Logic
– Min Zhao, Sachin S. Sapatnekar
- 2002
|
|
|
27.1 Achieving 550 MHz in an ASIC Methodology
– D. G. Chinnery, B. Nikolic, K. Keutzer
|
|
2
|
Achieving 550 MHz in an ASIC Methodology
– D. G. Chinnery, B. Nikoli, K. Keutzer
|
|
7
|
Clocking and Clocked Storage Elements in a Multi-Gigahertz Environment
– V. G. Oklobdzija
- 2003
|
|
|
Power Minimization by Simultaneous Dual-V Assignment and Gate-sizing
– Liqiong Wei, Kaushik Roy, Cheng-Kok Koh
- 2000
|
|
|
Novel Modeling and Optimization Techniques for Nano-Scale VLSI Designs
– Sanghamitra Roy
- 2008
|
|
|
Freescale Semiconductor
– Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla, Puneet Sharma
|
|
16
|
A New Statistical Optimization Algorithm for Gate Sizing
– Murari Mani, Michael Orshansky
|
|
17
|
Uncertainty-Aware Circuit Optimization
– Xiaoliang Bai, Chandu Visweswariah, Philip N. Strenski, David J. Hathaway
- 2002
|
|
7
|
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation
– I-min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
- 1999
|
|
9
|
Simultaneous Gate Sizing and Placement
– Wei Chen, Cheng-ta Hsieh, Massoud Pedram
- 2000
|
|
4
|
Efficient and Accurate Gate Sizing with Piecewise Convex Delay Models
– Hiran Tennakoon, Carl Sechen
- 2005
|
