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3
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BDDBased Testability Estimation of VHDL Designs
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Graph-based algorithms for Boolean function manipulation
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6
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Test Generation for Networks of Interacting FSMs Using Symbolic Techniques
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2
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Functional Design for Testability of Interacting Finite State Machines
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9
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A Unifying Methodology for Intellectual Property and Custom Logic Testing
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10
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On removing redundancy in sequential circuits
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26
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Testing embedded cores using partial isolation rings
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2
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On the modelling and testing of vhdl behavioral descriptions of sequential circuits
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2
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CUDD: CU decision diagram package, version 2.1.2
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1
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Definition of methodology for testability analysis at the RTL and CDFG levels requirement specs for functional pattern quality evaluator. Technical Report of Deliverable 2.3.A, Esprit project n.20616 - REQUEST
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22
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Testability Analysis and Improvement from VHDL Behavioral Specifications
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36
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Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration
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9
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On achieving a complete fault coverage for sequential machines using the transition fault model
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7
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FsmTest: Functional Test Generation for Sequential Circuits
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16
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A functional fault model for sequential machines
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36
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A System for Sequential Circuit Synthesis
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