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Exploring Relationships Among Several Testabilities
– Shangzhi Sun, David H. C. Du, Duenren Liu
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A Complete Testing Strategy Based on Interacting and Hierarchical FSMs
– F. Fummi, D. Sciuto
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7
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FsmTest: Functional Test Generation for Sequential Circuits
– G. Buonanno, F. Fummi, D. Sciuto, F. Lombardi
- 1996
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Dynamic Scan Testing: A New Paradigm - Part 3
– Clay Gloster
- 1993
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Simplifying Sequential Gate-Level Test Generation Through Exploitation of High-Level Information
– F. Ferrandi, F. Fummi, E. Macii, M. Poncino, D. Sciuto
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6
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Latch Redundancy Removal Without Global Reset
– Shaz Qadeer, Robert K. Brayton, Vigyan Singhal, Carl Pixley
- 1996
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Choice of Tests for Logic Verification and Equivalence Checking and the Use of Fault Simulation
– Vishwani Agrawal Bell
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1
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Probabilistic Analysis of Algorithms for Stuck-at Test Generation in PLAs
– John Franco
- 1995
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5
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Multiple Faults: Modeling, Simulation and Test
– Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
- 2002
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9
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On Random Pattern Generation with the Selfish Gene Algorithm for Testing
– Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal
- 2004
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12
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Identifying Sequentially Untestable Faults Using Illegal States
– David E. Long, Mahesh A. Iyer, Miron Abramovici
- 1995
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2
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Bounds on Pseudoexhaustive Test Length
– Rajagopalan Srinivasan, Eep K. Gupta, Melvin A. Breuer
- 1998
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8
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Deterministic Pattern Generation for Weighted Random Pattern Testing
– Birgit Reeb, Hans-joachim Wunderlich
- 1996
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1
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A Tool for Examining the Behaviour of Faults and Errors in Software Revision
– Martin Hiller, Martin Hiller, Martin Hiller, Martin Hiller
- 2000
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4
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The Pseudo-Exhaustive Test of Sequential Circuits
– Hans-Joachim Wunderlich, Sybille Hellebrand
- 1992
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Estimating Stuck Fault Coverage in Sequential Logic Using State Traversal and Entropy Analysis
– Soumitra Bose, Vishwani D. Agrawal
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1
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Fault Coverage Estimation for Non-Random Functional Input Sequences
– Soumitra Bose, Vishwani D. Agrawal
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3
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Grammar-Based Optimization of Synthesis Scenarios
– Andreas Kuehlmann, Lukas P.P.P. van Ginneken
- 1994
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2
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LOT: Logic Optimization with Testability - New Transformations for Logic Synthesis
– Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
- 1998
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