An Efficient Algorithm for Statistical Minimization of Total Power under Timing Yield Constraints (2005)

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by Murari Mani , Anirudh Devgan , Michael Orshansky
Venue:In DAC
Citations:38 - 0 self

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Constantine CaramanisRobust Algorithms for Area and Power Optimization of Digital Integrated Circuits under Variability – Murari Mani, Michael Orshansky Supervisor, Adnan Aziz, David Morton, David Pan, Murari Mani
19 A New Statistical Optimization Algorithm for Gate Sizing – Murari Mani, Michael Orshansky
25 Gate Sizing Using Incremental Parameterized Statistical Timing Analysis – M. R. Guthaus, N. Venkateswaran, C. Visweswariah, V. Zolotov - 2005
17 Joint-Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization – Murari Mani, Ashish K. Singh, Michael Orshansky - 2006
12 A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing – Seung-jean Kim, Stephen P. Boyd, Sunghee Yun, Dinesh D. Patil, Mark A. Horowitz - 2004
1 On the Futility of Statistical Power Optimization – Jason Cong, Puneet Gupta John Lee
Analysis and Optimization under Crosstalk and Variability in Deep Sub-Micron VLSI Circuits – Debjit Sinha - 2006
permission. Low Power Design Automation – David Graeme Chinnery, David Graeme Chinnery, David Graeme Chinnery
2 Low Power Design Automation – David Graeme Chinnery - 2006
1 A Heuristic Method for Statistical Digital Circuit Sizing – Stephen Boyd , Seung-Jean Kim , Dinesh Patil , Mark Horowitz
2 Evaluating the Effectiveness of Statistical Gate Sizing for Power Optimization – Nadathur Satish, Kaushik Ravindran, Matthew Moskewicz, David Chinnery, Kurt Keutzer - 2005
Evaluating Statistical Power Optimization – Jason Cong, Puneet Gupta, John Lee, Student Member
28 Minimization of Dynamic and Static Power Through Joint Assignment of Threshold Voltages and Sizing Optimization – David Nguyen, Abhijit Davare, Michael Orshansky, David Chinnery, On Thompson, Kurt Keutzer - 2003
3 Probabilistic Dual-Vth Leakage Optimization under Variability – Azadeh Davoodi, Ankur Srivastava - 2005
28.3 Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology – Seung Hoon Choi, Bipul C. Paul, Kaushik Roy
3 Optimization objectives and models of variation for statistical gate sizing – Matthew R. Guthaus, Natesan Venkateswaran, Dennis Sylvester - 2005
A New Method for Design of Robust Digital Circuits – unknown authors
12 A new method for design of robust digital circuits – Dinesh Patil, Sunghee Yun, Seung-jean Kim, Alvin Cheung, Mark Horowitz, Stephen Boyd - 2005
1 Robust Gate Sizing via Mean Excess Delay Minimization – Jason Cong, John Lee, Lieven V