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## Towards Variation-Aware System-Level Power Estimation of DRAMs: An Empirical Approach

### Citations

619 |
SimpleScalar: An Infrastructure for Computer System Modeling.
- Austin, Larson, et al.
- 2002
(Show Context)
Citation Context ...selected MediaBench applications [33] including: (1) Ray Tracing, (2) EPIC Encoder, (3) JPEG Encoder, and (4) GSM Decoder. These applications were independently executed on the SimpleScalar simulator =-=[36]-=- with a 16KB L1 D-cache, 16KB L1 I-cache, 128KB L2 cache and 64-byte cache line configuration. We filtered out the L2 cache misses meant for the DRAM and forwarded them through a DRAM controller [37],... |

249 | Parameter variations and impact on circuits and microarchitecture,”
- Borkar, Karnik, et al.
- 2003
(Show Context)
Citation Context ...ations on power consumption, for all system components, for an accurate system power analysis. In the case of processors, many solutions have been proposed, both by vendors and academia that estimate =-=[5, 6]-=- and even help mitigate [7,8], the expected performance and power impact. However, when it comes to DRAMs, vendors merely sort the memories into discrete speed-bins and furnish one set of worst-case c... |

40 |
Understanding the Energy Consumption of Dynamic Random Access Memories,”
- Vogelsang
- 2010
(Show Context)
Citation Context ... power estimation, many power models have been proposed. Among the circuit-level models, CACTI 5 [22] was proposed for embedded DRAMs, Rambus presented a circuit-level open-source DRAM power model in =-=[18]-=- and Weis et al. employed a SPICE based model in [19] for 3D-stacked DRAMs. At the system-level, Micron presented a datasheet-based power model in [21] and Chandrasekar et al., proposed a transaction-... |

39 | Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach
- Cho, Clark
- 2005
(Show Context)
Citation Context ...bsolutely essential to employ highly accurate power models and energy estimates for every component in the system, including processors and DRAMs. Unfortunately, with the impact of process variations =-=[3, 4]-=- on power consumption scaling significantly at technologies below 90nm, existing power models are becoming less and less accurate, while worst-case power estimates are just too pessimistic to use. Hen... |

32 |
C.: RAPL: memory power estimation and capping.
- David, Gorbatov, et al.
- 2010
(Show Context)
Citation Context ... DRAMs, Intel observed performance degradation and power variation in DRAM memories in [11,12] and suggested performance throttling to maintain an average power budget assuming datasheet estimates in =-=[15]-=-, as a work-around to this problem. M. Gottscho et al. in [13] also observed variations of around 15% in power consumption across several 1GB DIMMs from the same vendor and around 20% across different... |

30 |
Memory Systems: Cache,
- Jacob
- 2007
(Show Context)
Citation Context ...ulated DRAM cross-section. We modeled the memory cell architecture (of 6F 2 area), the equalization circuit, the wordline driver, and the sense amplifier using the designs suggested in [18], [25] and =-=[26]-=-. The baseline DRAM configuration targets a 1Gb DDR31066 (533MHz) x8 memory with core timings of 7-7-7 cc (refer Section 4.1) at 45nm. We chose 45nm, since it is the common technology node employed by... |

26 | Variation-aware dynamic voltage/frequency scaling. In: High Performance Computer Architecture,
- Herbert, Marculescu
- 2009
(Show Context)
Citation Context ...bal device parameters. As expected, the active (dynamic) DRAM currents and frequency increased linearly, while the leakage currents increased exponentially against the variations in the Vth parameter =-=[34,35]-=-. Hence, we analyzed the variations in leakage currents on the natural logarithmic scale [34] to obtain the σ values of their distributions corresponding to those of the Vth parameter. The variations ... |

21 |
Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging,” in
- Tschanz, Nam, et al.
- 2007
(Show Context)
Citation Context ...or all system components, for an accurate system power analysis. In the case of processors, many solutions have been proposed, both by vendors and academia that estimate [5, 6] and even help mitigate =-=[7,8]-=-, the expected performance and power impact. However, when it comes to DRAMs, vendors merely sort the memories into discrete speed-bins and furnish one set of worst-case current measures per speed-bin... |

16 | Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness,”
- Ye, Liu, et al.
- 2008
(Show Context)
Citation Context ...his, we vary global device parameters such as channel length, channel mobility, and oxide thickness and the local device threshold voltage (Vth) (primarily the variations in line edge roughness (LER) =-=[31]-=-), besides the interconnect parameters including wire width and wire thickness, within pre-defined variation ranges. We obtained the variability ranges (scaling metric (σ) in the corresponding Gaussia... |

14 | Architectures and modeling of predictable memory controllers for improved system integration
- Akesson, Goossens
(Show Context)
Citation Context ... [36] with a 16KB L1 D-cache, 16KB L1 I-cache, 128KB L2 cache and 64-byte cache line configuration. We filtered out the L2 cache misses meant for the DRAM and forwarded them through a DRAM controller =-=[37]-=-, which generated the memory commands. We also employed the power-down mode conservatively [38] during the idle periods. We compare the energy estimates, when employing the nominal (μ), datasheet (DS)... |

11 |
Energy Efficiency for Information Technology: How to Reduce Power Consumption in Servers and Data Centers.
- Minas, Ellison
- 2009
(Show Context)
Citation Context ...applications. 1. INTRODUCTION DRAM memories account for a significant share of any system’s power and energy consumption, be it battery-driven mobile devices [1] or high-performance computing servers =-=[2]-=-. With system power and energy budgets getting tighter, it becomes absolutely essential to employ highly accurate power models and energy estimates for every component in the system, including process... |

9 | Power variability in contemporary DRAMs
- Gottscho, Kagalwalla, et al.
- 2012
(Show Context)
Citation Context ...ying the datasheet measures. Unfortunately, such current distributions are not provided for all DRAMs, and only worst-case measures are given in vendor datasheets [10]. Intel in [11,12] and others in =-=[13,14]-=- observed similar power variation in DRAM memories and suggested different techniques to work around this problem [14–17]. However, there are no known realistic models or studies that estimate the act... |

9 |
ViPZonE: OS-Level Memory Variability-Driven Physical Address Zoning for Energy Savings
- Bathen
(Show Context)
Citation Context ...onsumption across several 1GB DIMMs from the same vendor and around 20% across different vendors, although they did not establish the causes for the observed extent of variations. L. Bathen et al. in =-=[16, 17]-=- employed these observations by [13], and suggested memory mapping and partitioning solutions to exploit this variability. S. Desai et al. in [14] on the other hand, performed Monte-Carlo analysis on ... |

7 |
Multi-core for mobile phones, in
- Berkel
- 2009
(Show Context)
Citation Context ... current measures for a set of MediaBench applications. 1. INTRODUCTION DRAM memories account for a significant share of any system’s power and energy consumption, be it battery-driven mobile devices =-=[1]-=- or high-performance computing servers [2]. With system power and energy budgets getting tighter, it becomes absolutely essential to employ highly accurate power models and energy estimates for every ... |

7 |
Design Space Exploration of 3D-stacked DRAMs,” in
- Weis
- 2011
(Show Context)
Citation Context ...ed. Among the circuit-level models, CACTI 5 [22] was proposed for embedded DRAMs, Rambus presented a circuit-level open-source DRAM power model in [18] and Weis et al. employed a SPICE based model in =-=[19]-=- for 3D-stacked DRAMs. At the system-level, Micron presented a datasheet-based power model in [21] and Chandrasekar et al., proposed a transaction-based power model in [20] that also uses datasheet me... |

5 |
Process variation aware dram design using block based adaptive body biasing algorithm
- Desai, Roy, et al.
- 2012
(Show Context)
Citation Context ...ying the datasheet measures. Unfortunately, such current distributions are not provided for all DRAMs, and only worst-case measures are given in vendor datasheets [10]. Intel in [11,12] and others in =-=[13,14]-=- observed similar power variation in DRAM memories and suggested different techniques to work around this problem [14–17]. However, there are no known realistic models or studies that estimate the act... |

5 | Improved Power Modeling of DDR SDRAMs,” in
- Chandrasekar
- 2011
(Show Context)
Citation Context ...uate our proposed solution by deriving the current distributions for Micron’s 2Gb DDR3-1600-x16 memories [10] based on the the Monte-Carlo analysis, and employing them with a system-level power model =-=[20,23]-=- to show significant differences between typical and worst-case datasheet current measures and the corresponding energy estimates (up to 28%) for four MediaBench applications [33]. 2. RELATED WORK Whe... |

5 |
DRAMPower: Open-source DRAM power and energy estimation tool
- Chandrasekar, Weis, et al.
(Show Context)
Citation Context ...uate our proposed solution by deriving the current distributions for Micron’s 2Gb DDR3-1600-x16 memories [10] based on the the Monte-Carlo analysis, and employing them with a system-level power model =-=[20,23]-=- to show significant differences between typical and worst-case datasheet current measures and the corresponding energy estimates (up to 28%) for four MediaBench applications [33]. 2. RELATED WORK Whe... |

3 |
et al., A 6F 2 Buried Wordline DRAM Cell for 40nm and Beyond
- Schloesser
(Show Context)
Citation Context ...f the simulated DRAM cross-section. We modeled the memory cell architecture (of 6F 2 area), the equalization circuit, the wordline driver, and the sense amplifier using the designs suggested in [18], =-=[25]-=- and [26]. The baseline DRAM configuration targets a 1Gb DDR31066 (533MHz) x8 memory with core timings of 7-7-7 cc (refer Section 4.1) at 45nm. We chose 45nm, since it is the common technology node em... |

3 |
Run-Time Power-Down Strategies for Real-Time SDRAM Memory Controllers
- Chandrasekar
(Show Context)
Citation Context ...ion. We filtered out the L2 cache misses meant for the DRAM and forwarded them through a DRAM controller [37], which generated the memory commands. We also employed the power-down mode conservatively =-=[38]-=- during the idle periods. We compare the energy estimates, when employing the nominal (μ), datasheet (DS) and realistic μ+2σ IDD measures from Table 5, since this covers more than 85% of the memories ... |

2 |
3-sigma Power Analysis Methodology
- Intel
(Show Context)
Citation Context ...the power models employing the datasheet measures. Unfortunately, such current distributions are not provided for all DRAMs, and only worst-case measures are given in vendor datasheets [10]. Intel in =-=[11,12]-=- and others in [13,14] observed similar power variation in DRAM memories and suggested different techniques to work around this problem [14–17]. However, there are no known realistic models or studies... |

1 |
An Empirical Study of Performance and Power Scaling of Low Voltage DDR3
- Ji
(Show Context)
Citation Context ...the power models employing the datasheet measures. Unfortunately, such current distributions are not provided for all DRAMs, and only worst-case measures are given in vendor datasheets [10]. Intel in =-=[11,12]-=- and others in [13,14] observed similar power variation in DRAM memories and suggested different techniques to work around this problem [14–17]. However, there are no known realistic models or studies... |

1 |
Statistical Compact Modeling of Variations in Nano MOSFETs
- Lin
(Show Context)
Citation Context ...onding Gaussian distributions) for these parameters from the ITRS technology requirements on Design for Manufacturability [29] and Modeling and Simulation [30] and the variation models of transistors =-=[31,32]-=-. We also introduce spatial-correlations in the variations among neighboring transistors, due to expected similarity in the parametric variations. Using these variability values, we performed Monte-Ca... |

1 |
Leakage and Process Variation Effects
- Keshavarzi
- 2002
(Show Context)
Citation Context ...bal device parameters. As expected, the active (dynamic) DRAM currents and frequency increased linearly, while the leakage currents increased exponentially against the variations in the Vth parameter =-=[34,35]-=-. Hence, we analyzed the variations in leakage currents on the natural logarithmic scale [34] to obtain the σ values of their distributions corresponding to those of the Vth parameter. The variations ... |