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## www.mdpi.com/journal/jlpea Sub-Threshold Standard Cell Sizing Methodology and Library Comparison (2013)

### Citations

117 |
The sum of log-normal probability distributions in scatter transmission systems,”
- Fenton
- 1960
(Show Context)
Citation Context ...of � parallel-connected transistors is the sum of their Log-Normal current distributions. The sum of Log-Normal distributions with the same variance can be approximated by one Log-Normal distribution =-=[21]-=-. A correlation factor �� for ��� needs to be introduced to improve the accuracy of the model. This correlation factor was not needed in series-connected transistors because in that case the source-bu... |

101 | Modeling and Sizing for Minimum Energy Operation in Subthreshold Circuits”,
- Calhoun, Wang, et al.
- 2005
(Show Context)
Citation Context ...aries. The results are shown in Section 5. Section 6 concludes the paper. 2. Sub-Threshold Cell Sizing Methodology Several relevant research results have been presented about sub-threshold sizing. In =-=[3,4]-=-, the authors calculate the optimum supply voltage to minimize energy consumption. It is also claimed that, theoretically, minimum sized cells are optimal for energy reduction. In this paper it is sho... |

70 |
Lognormal distributions: Theory and applications,
- Crow, Shimizu
- 1988
(Show Context)
Citation Context ...hreshold current distribution will not guarantee a robust behavior in the sub-threshold regime. We consider the ��� as a Normal distribution and model the distribution of the transistor current using =-=[18,19]-=- as follows: ���� � �� � � ��.� � � � ��� � ��� ��� ���������� �� ��� � ����� ���� � � ��������� ������ �1������� � �1 � � ���� � � where ��� stands for the mean value and ����� stands for the standar... |

61 |
Sub-Threshold Design for Ultra Low-Power Systems.
- Wang, Calhoun, et al.
- 2006
(Show Context)
Citation Context ...nt is the parasitic leakage, ideally zero. By reducing the voltage supply to sub-threshold, and by letting the transistor operate in weak inversion, the power consumption can be reduced quadratically =-=[16]-=-. Transistors operating in the sub-threshold regime obey an exponential dependence on the gate drive voltage [8]: ���� � � ��.��� ������� � �� �1 � � ���� � � (1) where � is the mobility; � is the oxi... |

54 |
RT-Level ITC'99 Benchmarks and First ATPG Results,
- Corno, Reorda, et al.
- 2000
(Show Context)
Citation Context ... DelayJ. Low Power Electron. Appl. 2013, 3 245 5. Circuit Synthesis Comparisons 5.1. ITC B14 Benchmark We look here first in detail at synthesis results of the B14 circuit from ITC benchmark circuit =-=[25]-=-. We extracted the critical paths generated by each different library at 0.3 V, and then applied 1000 Monte Carlo simulations are used to generate the delay distributions of each critical path to comp... |

38 |
A 65 nm sub-vt microcontroller with integrated sram and switched capacitor dcdc converter,” Solid-State Circuits,
- Kwong, Ramadass, et al.
- 2009
(Show Context)
Citation Context ...aries. The results are shown in Section 5. Section 6 concludes the paper. 2. Sub-Threshold Cell Sizing Methodology Several relevant research results have been presented about sub-threshold sizing. In =-=[3,4]-=-, the authors calculate the optimum supply voltage to minimize energy consumption. It is also claimed that, theoretically, minimum sized cells are optimal for energy reduction. In this paper it is sho... |

30 | Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits,”
- Kwong, Chandrakasan
- 2006
(Show Context)
Citation Context ...� �� �1������������ /�� where ���� is the width of one single transistor, ��� �����.����1 � � ���� � � and �� ∝���������. The equivalent width for parallel transistors can be calculated from Equation =-=(7)-=- [1]. (7) � ���� ������ ��� ���� ��� �� �� (8)J. Low Power Electron. Appl. 2013, 3 240 Hence the width of a single transistor, which has the same mean current as the one of � transistors in parallel,... |

14 |
Matching properties of mos transistors,” J. Solid-State Circuits,
- Pelgrom, Duinmaijer, et al.
- 1989
(Show Context)
Citation Context ...heir timing variation at 0.3 V. The results of the delay, variation and area of the cells are shown in Figure 6. The marker size shows the area of the cell. As known, bigger cells have less variation =-=[24]-=-. However, in the figure, this is not always true for all the cells; most of the cells lie in the standard deviation/mean range from 50% to 70%. There is no clear indication that, increasing the area ... |

11 |
Static Timing Analysis for Nanometer Designs: A Practical Approach
- Bhasker, Chadha
- 2009
(Show Context)
Citation Context ...s is used for the 40 nm library, and ELC is used for the 90 nm one. The simulation engine is Spectre. The results of the library characterization are stored according to the commercial liberty format =-=[23]-=-. The timing information of each pin of each cell is presented in four matrices: rise time represents the rising slew, rise transition represents the transition time when the output rises. Similarly, ... |

10 | Utilizing reverse shortchannel effect for optimal subthreshold circuit design,"
- Kim, Keane, et al.
- 2007
(Show Context)
Citation Context ...ies is carried out using both a CMOS 90 nm and a CMOS 40 nm low power process. ITC benchmark circuit synthesis results are presented as well. Unlike conventional “super-threshold” cell sizing methods =-=[8,9]-=-, the proposed balancing-based sizing method focuses on the statistical distribution of the drain-source current, rather than the current itself. In the proposed approach, the variation of the current... |

10 |
Technology flavor selection and adaptive techniques for timing-constrained 45 nm subthreshold circuits,”
- Bol, Flandre, et al.
- 2009
(Show Context)
Citation Context ...eoretically, minimum sized cells are optimal for energy reduction. In this paper it is shown that under speed constraints, and when process variability is taken into account, this is not the case. In =-=[11]-=-, the authors explain the benefit of technology choices, power supply scaling, and body bias adaptability for circuits working in the sub-threshold regime. It is implied that standard cell timing coul... |

7 |
Nanometer MOSFET Effects on the Minimum-Energy Point of 45nm Subthreshold Logic
- Bol, Kamel, et al.
- 2009
(Show Context)
Citation Context ..., 3 239 1/�� times smaller with regard to the upper PMOS (lower NMOS) transistors. The variation of the current stack can be written as: ����� ������ ��� ������ ∝ ��������1� �1��1������1�� � ���� � � =-=(6)-=- Equation (6) helps to understand how many transistors can be stacked for given current variation and area constraints. Ultimately, this is a very important criterion for robust operation. To quantify... |

6 |
A 0.27 V 30 MHz 17.7 nJ/transform 1024-pt complex FFT core with super-pipelining
- Seok, Jeon, et al.
- 2011
(Show Context)
Citation Context ...� ��������� ����������� ������������ �� ��∑ � ��� � �� ��� ����� � ��� ������ ��� ��������� ����� �1�� � �� ������ where � ��� is also a technology dependent fitting parameter. With Equations (4) and =-=(5)-=-, one can easily derive the optimal stack width ratio for the stack’s maximum current or minimum current spread. To achieve the maximum current, the lower PMOS (upper NMOS) transistor needs to be size... |

6 | Subthreshold logical effort: A systematic framework for optimal subthreshold device sizing
- Keane, Eom, et al.
- 2006
(Show Context)
Citation Context ...per �N � 1� PMOS transistors [lower �N�1� NMOS transistors] have a similar impact on the current behavior of the stack. Therefore, let these �N � 1� transistors have equal sizes. Using the results of =-=[9,20]-=- to calculate the equivalent transistor width of the stack, W �����, the mean current of � transistors in a stack is calculated as follows [1] ��� ������ �� �� ������ � ����� � ��� � �������∑��� � �� ... |

4 |
Rozon,"UDSM subthreshold leakage model for NMOS transistor stacks
- Al-Hertani, Al-Khalili, et al.
- 2008
(Show Context)
Citation Context ...per �N � 1� PMOS transistors [lower �N�1� NMOS transistors] have a similar impact on the current behavior of the stack. Therefore, let these �N � 1� transistors have equal sizes. Using the results of =-=[9,20]-=- to calculate the equivalent transistor width of the stack, W �����, the mean current of � transistors in a stack is calculated as follows [1] ��� ������ �� �� ������ � ����� � ��� � �������∑��� � �� ... |

2 |
de Gyvez, J.P., "Standard cell sizing for subthreshold operation
- Liu, Ashouei, et al.
- 2012
(Show Context)
Citation Context ...ircuits. The problem is that process variability severely impacts the performance of circuits operating in the sub-threshold domain. In this paper, we evaluate the sub-threshold sizing methodology of =-=[1,2]-=- on 40 nm and 90 nm standard cell libraries. The concept of the proposed sizing methodology consists of balancing the mean of the sub-threshold current of the equivalent N and P networks. In this pape... |

2 |
Analysis and mitigation of variability in subthreshold design
- Hanson, Blaauw, et al.
- 2005
(Show Context)
Citation Context ...hreshold current distribution will not guarantee a robust behavior in the sub-threshold regime. We consider the ��� as a Normal distribution and model the distribution of the transistor current using =-=[18,19]-=- as follows: ���� � �� � � ��.� � � � ��� � ��� ��� ���������� �� ��� � ����� ���� � � ��������� ������ �1������� � �1 � � ���� � � where ��� stands for the mean value and ����� stands for the standar... |

1 |
Library Tuning for Subthreshold Operation
- Liu, Gyvez, et al.
- 2012
(Show Context)
Citation Context ... that directly affects the functional correctness and the minimum V �� . In the proposed sizing methodology, the ratio of the pull-up to pull-down transistors is determined by the balance between the =-=(2)-=-J. Low Power Electron. Appl. 2013, 3 237 current distributions of the PMOS and NMOS transistors. The difference with regard to the conventional sizing approach is that the current spread caused by th... |

1 |
A 40 nm Inverse-Narrow-Width-Effect-Aware Sub-Threshold Standard Cell Library
- Jun, Jayapal, et al.
- 2011
(Show Context)
Citation Context ...es, since in the sub-threshold regime, increasing the channel length has a positive impact on timing and timing variation [8]. Therefore, by increasing the transistor’s length and by tuning the width =-=[10]-=- we are able to size the cells in the sub-threshold regime with two degrees of freedom. The second optimization approach, width tuning only, targets better timing and variation from the sub-threshold ... |

1 |
low-carbon wireless sensor nodes. Solid-State Circ
- Bol, Vos, et al.
(Show Context)
Citation Context ...the maximum active current for both the NMOS and PMOS transistors. Only the transistors on slower timing arcs are allowed to be upsized, the ones on faster timing arcs are down sized to save area. In =-=[12]-=-, a standard cell library in 65 nm is presented, where by upsizing the channel length of all transistors in a given cell, the energy per operation value is reduced by about 15%. In this paper, the sta... |

1 |
Multiobjective Optimization for Transistor Sizing Sub-threshold CMOS Logic Standard Cells
- Blesken, Lu, et al.
- 2010
(Show Context)
Citation Context ... energy per operation value is reduced by about 15%. In this paper, the standard cells are tuned individually, with various length and width selections to have balanced transition currents. Reference =-=[13]-=- presents a searching algorithm based on multiple objectives through a free space search to optimize one cell. The approach is exhaustive and suitable for single cells, but the searching effort is ver... |

1 |
A 45nm CMOS 0.35v-optimized Standard Cell Library for Ultra-low power Applications
- Abouzeid, Clerc, et al.
- 2009
(Show Context)
Citation Context ...cells, but the searching effort is very large for a complete library. Unlike [11], our optimization targets balancing the mean P and N currents and takes into account the impact of process spread. In =-=[14]-=-, a 45 nm standard cell library optimized for 0.35 V is proposed. The proposed PMOS-to-NMOS transistor ratio optimization is based on the optimal energy-delay product, not on balanced rise and fall ti... |

1 |
Operation and Modeling of the Mos Transistor (The Oxford
- Tsividis
- 2004
(Show Context)
Citation Context ...on, a balancing based sizing methodology is developed for robust standard cell design. 2.1. Sub-Threshold Current Distribution Model The sub-threshold region is often called the weak inversion region =-=[15]-=-, partly because in the sub-threshold region, the transistor is neither completely turned on nor turned off. In digital circuits, the sub-threshold current is the parasitic leakage, ideally zero. By r... |

1 |
Star-Hspice User's Manual; Synopsys: Mountain View
- Avant
- 2000
(Show Context)
Citation Context ...s the thermal voltage. ��� is the gate to source voltage; ��� is the drain to source voltage; ��� is the threshold voltage, consists of zero biasing voltage, terminal voltages and device size effects =-=[17]-=-. From Equation (1), one can see that the current has an exponential relationship with the gate-to-source voltage and the threshold voltage of the transistor. In sub-threshold, the probability distrib... |

1 |
Variability Aware Cell Library Optimization for Reliable Sub-Threshold Operation
- Gemmeke, Ashouei
- 2012
(Show Context)
Citation Context ...e run for 1 to 6 NMOS transistors connected in parallel, with a total width of 1.20 μm. The simulation and calculation results are shown in Table 2. It is worth observing these results in more detail =-=[22]-=-. Namely, the joint correlated Log-Normal distribution indicates that the mean current is bigger than that of the uncorrelated sum of individual transistor currents [18,21]. This implies that for the ... |