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## Low Power Implementation of a Turbo-Decoder on Programmable Architectures (2001)

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### Other Repositories/Bibliography

Venue: | In Proc. ASP-DAC ’01 |

Citations: | 9 - 4 self |

### Citations

1776 | Near Shannon Limit Error-Correcting Coding and Decoding
- Berrou, Glavieux, et al.
- 1993
(Show Context)
Citation Context ... the channel decoder to correct the errors. A common measure for the performance of a coding scheme is the bit-error-rate (BER) as a function of the signal-to-noise ratio (SNR) E s =N 0 . Turbo-Codes =-=[1]-=-, first published in 1993, show the best forward error correction performance known up to now. Thus Turbo-Codes became part of the third generation wireless systems (UMTS) [2] standard which offers hi... |

610 | Iterative Decoding of Binary Block and Convolutional Codes”,
- Hagenauer, Papke
- 1996
(Show Context)
Citation Context ...at the channel charactistics improve temporarily compared to the working point, the iterations can be stopped as soon as the overall quality of the decoded bits is sufficient. Techniques presented in =-=[10]-=-, [11] can be used to derive such a criterion. However, the most efficient technique is the use of cyclic redundancy codes (CRC) [12]. This requires that the data frames are protected by a CRC-check. ... |

563 | Scheduling for reduced CPU energy.
- Weiser, Welch, et al.
- 1994
(Show Context)
Citation Context ...essors like the Transmeta processor enter mainstream technology, this technique will become more and more important. Recent results on the theory and technical viability of DVS have been published in =-=[6]-=-, [7], [8], [9]. DVS can only be beneficial if the maximum CPU speed is needed just in a fraction of time. Thus, a fixed iteration implementation of a Turbo-decoder processing at maximum speed can not... |

403 | Voltage scheduling problem for dynamically variable voltage processors.
- Ishihara, Yasuura
- 1998
(Show Context)
Citation Context ...e the Transmeta processor enter mainstream technology, this technique will become more and more important. Recent results on the theory and technical viability of DVS have been published in [6], [7], =-=[8]-=-, [9]. DVS can only be beneficial if the maximum CPU speed is needed just in a fraction of time. Thus, a fixed iteration implementation of a Turbo-decoder processing at maximum speed can not benefit f... |

303 | The simulation and evaluation of dynamic voltage scaling algorithm
- Pering, Burd, et al.
- 1998
(Show Context)
Citation Context ...s like the Transmeta processor enter mainstream technology, this technique will become more and more important. Recent results on the theory and technical viability of DVS have been published in [6], =-=[7]-=-, [8], [9]. DVS can only be beneficial if the maximum CPU speed is needed just in a fraction of time. Thus, a fixed iteration implementation of a Turbo-decoder processing at maximum speed can not bene... |

237 | A dynamic voltage scaled microprocessor system.
- Burd, Pering, et al.
- 2000
(Show Context)
Citation Context ... Transmeta processor enter mainstream technology, this technique will become more and more important. Recent results on the theory and technical viability of DVS have been published in [6], [7], [8], =-=[9]-=-. DVS can only be beneficial if the maximum CPU speed is needed just in a fraction of time. Thus, a fixed iteration implementation of a Turbo-decoder processing at maximum speed can not benefit from D... |

154 | Optimal and suboptimal maximum a posteriori algorithms suitable for turbo decoding,”
- Robertson, Hoeher, et al.
- 1997
(Show Context)
Citation Context ... an interleaver (INT), and two deinterleavers (DE). These are the building blocks of the iterative Turbo-decoding process. Details of the Turbo-decoder system model and the MAP algorithm are given in =-=[1-=-5] and [16]. DE INT c DE MAP2 + + c MAP1 ~y s ~ 2 ~y 1p ~y s int ~y 2p int ~z 2 int ~z 1 ~ 1 Fig. 2. Turbo-decoder 0 2 4 6 8 10 12 14 16 1 2 3 4 5 Iteration decodable frames undecodable frames Fig. ... |

116 |
Wideband CDMA for Third Generation Mobile Communications,
- Ojanperä, Prasad
- 1999
(Show Context)
Citation Context ...ber of iterations is increased. The last case is especially important in packet oriented network protocols like TCP/IP. Intelligent power control mechanisms as in wideband CDMA (air interface in UMTS =-=[3]) try to c-=-ompensate this fading, however these techniques are imperfect and induce latency. This "dynamic throughput behavior" can be exploited to save power. To achieve this, stopping criteria on sys... |

59 |
Two simple stopping criteria for turbo decoding,”
- Shao, Lin, et al.
- 1999
(Show Context)
Citation Context ... channel charactistics improve temporarily compared to the working point, the iterations can be stopped as soon as the overall quality of the decoded bits is sufficient. Techniques presented in [10], =-=[11]-=- can be used to derive such a criterion. However, the most efficient technique is the use of cyclic redundancy codes (CRC) [12]. This requires that the data frames are protected by a CRC-check. Depend... |

47 |
A novel ARQ technique using the turbo coding principle,"
- Narayanan, Stüber
- 1997
(Show Context)
Citation Context ...quality of the decoded bits is sufficient. Techniques presented in [10], [11] can be used to derive such a criterion. However, the most efficient technique is the use of cyclic redundancy codes (CRC) =-=[12]-=-. This requires that the data frames are protected by a CRC-check. Depending on the CRC-check result, the iteration can be stopped or has to be continued. CRC-checks are common techniques used in stan... |

23 |
Low complexity turbo-like codes
- Divsalar, Dolinar, et al.
- 2000
(Show Context)
Citation Context ...C-controlled Intelligent Cancellation Optimum Fig. 4. Normalized number of iterations of stop-criteria it is easier to calculate, it is preferred. Recently our approach was confirmed theoretically by =-=[17]-=-. Fig. 4 shows the results of our cancellation method. The normalized number of iterations is compared to a CRC-controlled scheme. Our method reduces the number of iterations over the complete SNR ran... |

22 | Turbo-decoding without SNR estimation
- Worm, Hoeher, et al.
- 2000
(Show Context)
Citation Context ...oved channel characteristics are considered. Thus a lot of optimization potential is lost. The DVS heuristic is based on SNR estimates, but SNR estimation in the context of Turbo-codes is unnecessary =-=[14]-=-. The paper lacks simulations of realistic wireless environment scenarios and power models. III. NEW APPROACH We consider packet oriented network protocols such as TCP/IP. In these protocols, the numb... |

7 | New Iterative (\Turbo") Decoding Algorithms
- Hoeher
- 1997
(Show Context)
Citation Context ...leaver (INT), and two deinterleavers (DE). These are the building blocks of the iterative Turbo-decoding process. Details of the Turbo-decoder system model and the MAP algorithm are given in [15] and =-=[16]-=-. Mean of LLRs 16 14 12 10 8 6 4 2 0 Fig. 2. Turbo-decoder 1 2 3 4 5 decodable frames Iteration undecodable frames Fig. 3. Mean of LLRs for decodable and undecodable frames at SNR = -2.00 dB If not ot... |

6 |
High Performance DSPs { What's Hot and What's Not
- Ackland, Nicol
- 1998
(Show Context)
Citation Context ... a range of supply voltages and can vary their clock speed (f CLK ) and supply voltage (V DD ) at run time depending on actual throughput requirements ("Dynamic Voltage Scaling"). II. RELATE=-=D WORK In [5], dynamic -=-voltage scheduling (DVS) is referred to as "the most revolutionary low power technique to date" and is superior to a processor power-down mode due to the square dependency of the supply volt... |

5 |
Third Generation Partnership Projects
- 3GPP
(Show Context)
Citation Context ...) E s =N 0 . Turbo-Codes [1], first published in 1993, show the best forward error correction performance known up to now. Thus Turbo-Codes became part of the third generation wireless systems (UMTS) =-=[2]-=- standard which offers high data-rate services (up to 2MBit/s) for internet and multimedia applications. Turbo-Codes are also in discussion for other wireless standards, e. g. WLAN applications. Softw... |

5 |
Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage
- Leung, Tsui, et al.
(Show Context)
Citation Context ...addressed by current literature. Simply using an estimated channel SNR as a criterion is too coarse and may trash too many decodable blocks. Only one approach in literature applies DVS to Turbo-Codes =-=[13]-=-. CRC-protection is added to each data frame and is checked after every iteration. An ASAP (as-slow-as-possible) and an SNR-assisted DVS-heuristic is presented which adjusts the decoding speed and sup... |

2 |
Securcore processors
- CORPORATION
- 2011
(Show Context)
Citation Context ...either shutting down the processor or using dynamic voltage scheduling which is much more energy efficient. Recent developments in microprocessor technology, e. g. the Crusoe Processor from Transmeta =-=[4], off-=-er the possibility to operate over a range of supply voltages and can vary their clock speed (f CLK ) and supply voltage (V DD ) at run time depending on actual throughput requirements ("Dynamic ... |

2 |
New Iterative ("Turbo") Decoding Algorithms
- Hoeher
- 1997
(Show Context)
Citation Context ...leaver (INT), and two deinterleavers (DE). These are the building blocks of the iterative Turbo-decoding process. Details of the Turbo-decoder system model and the MAP algorithm are given in [15] and =-=[1-=-6]. DE INT c DE MAP2 + + c MAP1 ~y s ~ 2 ~y 1p ~y s int ~y 2p int ~z 2 int ~z 1 ~ 1 Fig. 2. Turbo-decoder 0 2 4 6 8 10 12 14 16 1 2 3 4 5 Iteration decodable frames undecodable frames Fig. 3. Mean o... |

1 |
Fossorier, "Two Simple Stopping Criteria for Turbo Decoding
- Shao, Lin, et al.
- 1999
(Show Context)
Citation Context ... channel charactistics improve temporarily compared to the working point, the iterations can be stopped as soon as the overall quality of the decoded bits is sufficient. Techniques presented in [10], =-=[11]-=- can be used to derive such a criterion. However, the most efficient technique is the use of cyclic redundancy codes (CRC) [12]. This requires that the data frames are protected by a CRC-check. Depend... |

1 |
Lucent Technologies, "StarCore DSP
- Motorola
- 2000
(Show Context)
Citation Context ...considered to quantify the advantage of our new DVS algorithm in combination with our cancellation critierion. The following processors were investigated: StarCore SC140 (Motorola/Lucent Technologies =-=[19]-=-) and Crusoe processor (Transmeta [4]). The Crusoe processor is a VLIW general-purpose microprocessor optimized for low power applications. It is reported to operate over a complete range of supply vo... |

1 |
High Performance DSPs
- Ackland, Nicol
- 1998
(Show Context)
Citation Context ...e over a range of supply voltages and can vary their clock speed (�� ) and supply voltage ( ��) atrun time depending on actual throughput requirements (“Dynamic Voltage Scaling”). II. RELATED WORK In =-=[5]-=-, dynamic voltage scheduling (DVS) is referred to as “the most revolutionary low power technique to date” and is superior to a processor power-down mode due to the square dependency of the supply volt... |