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## Dual Voltage Design for Minimum Energy Using

### Citations

377 | Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas,”
- Sakurai, Newton
- 1990
(Show Context)
Citation Context ...the supply voltage increases the gate delay exponentially in the subthreshold region, while the gate delay increase for the nominal voltage operation is polynomial following the alpha-power law model =-=[11]-=-, [15]. It means that positive slack inside a circuit is reduced quickly by assigning VDDL in subthreshold region. Thus, we can obtain the optimal VDDL close to VDDH and less VDDL gates from dual Vdd ... |

207 |
New generation of Predictive Technology Model for sub-45nm early design exploration.
- Zhao, Cao
- 2006
(Show Context)
Citation Context ...ulating slack time for all gates of a circuit is O(n), where n is total number of gates. Figure 1(a) shows the slack time distribution for c2670 ISCAS’85 benchmark circuit in PTM 90nm CMOS technology =-=[16]-=-. To quickly identify the possible VDDL gates on non-critical paths, we introduce an upper slack time (Su) that guarantees that any gate with slack time larger than Su will be free from timing violati... |

163 |
Clustered voltage scaling technique for low-power design’.
- Usami, Horowitz
- 1995
(Show Context)
Citation Context ...Vdd technique exploits time slacks in the circuit by assigning a lower supply voltage (VDDL) to gates on noncritical paths and a higher supply voltage (VDDH=Vdd) to gates on critical paths [2], [10], =-=[13]-=-, [14]. For maximizing power saving, an optimal lower supply voltage is determined such that it can be assigned to as many positive slack gates as possible without exceeding the critical path delay. H... |

61 |
Sub-Threshold Design for Ultra Low-Power Systems.
- Wang, Calhoun, et al.
- 2006
(Show Context)
Citation Context ...pply voltage increases the gate delay exponentially in the subthreshold region, while the gate delay increase for the nominal voltage operation is polynomial following the alpha-power law model [11], =-=[15]-=-. It means that positive slack inside a circuit is reduced quickly by assigning VDDL in subthreshold region. Thus, we can obtain the optimal VDDL close to VDDH and less VDDL gates from dual Vdd scheme... |

60 | Timing Verification and the Timing Analysis Program”,
- Hitchcock
- 1982
(Show Context)
Citation Context ...ion from MILP solution for minimum energy consumption. First, Our algorithm generates slack time distribution of a given circuit. We have developed an expanded version of static timing analysis (STA) =-=[7]-=-. For the output of gate i, let TPI(i) be the longest time for an event to arrive from a PI and TPO(i) be the longest time for an event to reach a PO. The delay of the longest path through gate i is g... |

60 |
Automated low-power technique exploiting multiple supply voltages applied to a media processor’,
- Usami, Igarashi, et al.
- 1998
(Show Context)
Citation Context ...chnique exploits time slacks in the circuit by assigning a lower supply voltage (VDDL) to gates on noncritical paths and a higher supply voltage (VDDH=Vdd) to gates on critical paths [2], [10], [13], =-=[14]-=-. For maximizing power saving, an optimal lower supply voltage is determined such that it can be assigned to as many positive slack gates as possible without exceeding the critical path delay. However... |

45 | Dynamic and leakage power reduction in MTCMOS circuits using an automated gate clustering technique.
- Anis, Areibi, et al.
- 2002
(Show Context)
Citation Context ... from [9] is dual Vdd selection conditions. Tc is critical path delay and given by the performance requirement, thus VDDH is selected from (7) in power supply domain V . Using a bin-packing technique =-=[1]-=- all gates must be assigned to one of power supply voltage in V from (8) and (9). MILP always guarantees that a dual Vdd circuit with the optimal VDDL and it assignments achieve minimum energy consump... |

37 | On gate level power optimization using dual-supply voltages,”
- Chen, Srivastava, et al.
- 2001
(Show Context)
Citation Context ...ce, a dual Vdd technique exploits time slacks in the circuit by assigning a lower supply voltage (VDDL) to gates on noncritical paths and a higher supply voltage (VDDH=Vdd) to gates on critical paths =-=[2]-=-, [10], [13], [14]. For maximizing power saving, an optimal lower supply voltage is determined such that it can be assigned to as many positive slack gates as possible without exceeding the critical p... |

34 |
T.Kuroda. Utilizing surplus timing for power reduction.
- Hamada
- 2001
(Show Context)
Citation Context ... supply voltage Vdd is developed to determine the optimal VDDL for maximum power saving, then VDDL assignments are executed to achieve lowest power consumption considering multiple voltage boundaries =-=[6]-=-, [10]. Most of dual Vdd techniques are based on heuristic greedy algorithms and applied to nominal operating circuits for lowering power consumption. For energy constrained applications, dual Vdd tec... |

21 |
Closing the power gap between ASIC & custom: tools and techniques for low power design
- Chinnery, Keutzer
- 2007
(Show Context)
Citation Context ...istic traversing the circuit from primary outputs to primary inputs in level order. Two heuristic algorithms have theoretical runtime complexity O(n 2 ), where n is total number of gates in a circuit =-=[4]-=-. Most researches have focused on improving power saving implementing their own greedy algorithms [2], [3], [11]. These are still heuristic approaches and provide a suboptimal solution for dual Vdd as... |

15 | Synthesis of low power cmos vlsi circuits using dual supply voltages.
- Sandararajan, Parhi
- 1999
(Show Context)
Citation Context ...e, a dual Vdd technique exploits time slacks in the circuit by assigning a lower supply voltage (VDDL) to gates on non-critical paths and a higher supply voltage (VDDH=Vdd) to gates on critical paths =-=[14]-=-, [2], [11], [15], [16]. For maximizing power saving, an optimal lower supply voltage is determined such that it can be assigned to as many positive slack gates as possible without exceeding the criti... |

14 | Linear programming for sizing, Vth and Vdd assignment
- Chinnery, Keutzer
- 2005
(Show Context)
Citation Context ...eger linear programs (MILP) [5] are widely used to optimize a circuit for minimizing power or energy consumption using sizing, multiple Vdd, multiple threshold voltage (Vth) and combinations of those =-=[4]-=-, [9], [12]. MILP searches global optimal solution for an objective function, minimize power, considering the entire design space. Thus, it may take huge time to optimize large circuits used in modern... |

9 | A New Algorithm for Improved VDD Assignment - Kulkarni, Srivastava, et al. - 2004 |

8 | Minimum Energy CMOS Design with Dual Subthreshold Supply and Multiple Logic-Level Gates,” in
- Kim, Agrawal
- 2011
(Show Context)
Citation Context ...tion for ISCAS’85 benchmark circuits shows energy saving up to 22.2% in subthreshold operation and 50.8% in nominal operation, which are the same as were obtained by the higher-complexity MILP method =-=[8]-=-, [9]. Computation time is reduced up to 44X compared to MILP. Our proposed algorithm has linear time complexity O(n) with total n number of gates of a circuit. A new slack-time based algorithm is use... |

8 |
Power Minimization using Simultaneous Gate
- Srivastava, Sylvester, et al.
(Show Context)
Citation Context ...r programs (MILP) [5] are widely used to optimize a circuit for minimizing power or energy consumption using sizing, multiple Vdd, multiple threshold voltage (Vth) and combinations of those [4], [9], =-=[12]-=-. MILP searches global optimal solution for an objective function, minimize power, considering the entire design space. Thus, it may take huge time to optimize large circuits used in modern VLSI syste... |

6 | True Minimum Energy Design Using Dual Below-Threshold Supply Voltages
- Kim, Agrawal
- 2011
(Show Context)
Citation Context ...linear programs (MILP) [5] are widely used to optimize a circuit for minimizing power or energy consumption using sizing, multiple Vdd, multiple threshold voltage (Vth) and combinations of those [4], =-=[9]-=-, [12]. MILP searches global optimal solution for an objective function, minimize power, considering the entire design space. Thus, it may take huge time to optimize large circuits used in modern VLSI... |

4 |
Gate level multiple supply voltage assignment algorithm for power optimization under timing constraint
- Chi, Lee, et al.
(Show Context)
Citation Context ...s use the backward traversal heuristic traversing the circuit from primary outputs in level order. Most researches have focused on improving power saving implementing their own greedy algorithms [2], =-=[3]-=-, [10]. These are still heuristic approaches and provide a suboptimal solution for dual Vdd assignment. Mixed integer linear programs (MILP) [5] are widely used to optimize a circuit for minimizing po... |