This paper introduces Embedded Deterministic Test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented. 1.

Continued advancements in fabrication technology and reductions in feature size create challenges in maintaining both manufacturing yield rates and long-term reliability of devices. Methods based on defect detection and reduction may not offer a scalable solution due to cost of eliminating contaminants in the manufacturing process and increasing chip complexity. This paper proposes to use the inherent redundancy available in existing and future chip microarchitectures to improve yield and enable graceful performance degradation in fail-in-place systems. We introduce a new yield metric called performance averaged yield ( ) which accounts both for fully functional chips and those that exhibit some performance degradation. Our results indicate that at 250nm we are able to increase the of a uniprocessor with only redundant rows in its caches from a base value of 85% to 98% using microarchitectural redundancy. Given constant chip area, shrinking feature sizes increases fault susceptibility and reduces the base to 60% at 50nm, which microarchitectural redundancy then increases to 99.6%.

A common approach for large industrial designs is to use logic built-in self-test (LBIST) followed by test data from an external tester. Because the fault coverage with LBIST alone is not sufficient, there is a need to top-up the fault coverage with additional deterministic test patterns from an external tester. This paper proposes a technique of combining LBIST and deterministic ATPG to form "hybrid test patterns" which merge pseudorandom and deterministic test data. Experiments have been done on the Motorola PowerPC TM microprocessor core to study the proposed hybrid test patterns. Hybrid test patterns provide several advantages: 1) can be applied using STUMPS architecture [Bardell 82] with a minor modification, 2) significantly reduce external test data stored in tester memory, 3) reduce the number of pseudo-random patterns by orders of magnitude, thus addressing power issues. 1. Introduction Logic built-in self-test (LBIST) is being increasingly used to tackle the test problems...

This paper introduces a finite memory compactor called convolutional compactor that provides compaction ratios of test responses in excess of 100x even for a very small number of outputs. This is combined with the capability to detect multiple errors, handling of unknown states, and the ability to diagnose failing scan cells directly from compacted responses. A convolutional compactor can be easily configured into a MISR that preserves most of these properties. Experimental results demonstrate the efficiency of compaction for several industrial circuits. 1.

1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-test. However, due to their reliance on random patterns, current logic BIST techniques are not able to deal with large designs without adding high test overhead. In this paper, we propose a functional self-test technique that is deterministic in nature. By targeting the structural test need of manageable components with the aid of processor functionality, this technique has the fault coverage advantage of deterministic structural testing and the at-speed advantage of functional testing. Most importantly, by relieving testers from test application, it enables at-speed testing of GHz processors with low speed testers. We have demonstrated our methodology on a simple accumulator-based microprocessor. The results show that with the proposed technique, we are able to apply high-quality at-speed tests with no test...

This paper presents' a new test resource partitioning scheme that is a hybrid approach between external testing and BIST. It reduces tester storage requirements' and tester bandwidth requirements' by orders' of magnitude compared to conventional external testing, but requires much less area overhead than a full BIST implementation providing the same fault coverage. The proposed approach is based on weighted pseudo-random testing and uses a novel approach for compressing and storing the weight sets'. Three levels' of compression are used to greatly reduce test costs'. No test points' or any modifications are made to the function logic. The proposed scheme requires adding only a small amount of additional hardware to the STUMPS architecture.

This paper presents a new compression method for embedded core-based system-on-a-chip test. In addition to the new compression method, this paper analyzes the three test data compression environ-ment (TDCE) parameters: compression ratio, area overhead and test application time, and explains the impact of the factors which influence these three parameters. The proposed method is based on a new Variable-length Input Huffman Coding scheme, which proves to be the key element that determines all the factors that influence the TDCE parameters. Extensive experimental comparisons show that, when compared to three previous approaches [1–3], which reduce some test data compression environment’s parameters at the expense of the others, the proposed method is capable of improving on all the three TDCE parameters simultaneously. 1

Abstract—A test solution for a complex system requires the design of a test access mechanism (TAM), which is used for the test data transportation, and a test schedule of the test data transportation on the designed TAM. An extensive TAM will lead to lower test-application time at the expense of higher routing costs, compared to a simple TAM with low routing cost but long testing time. It is also possible to reduce the testing time of a testable unit by loading the test vectors in parallel, thus increasing the parallelization of a test. However, such a test-time reduction often leads to higher power consumption, which must be kept under control since exceeding the power budget could damage the system under test. Furthermore, the execution of a test requires resources and concurrent execution of tests may not be possible due to resource or other conflicts. In this paper, we propose an integrated technique for test scheduling, test parallelization, and TAM design, where the test application time and the TAM routing are minimized, while considering test conflicts and power constraints. The main features of our technique are the efficiency in terms of computation time and the flexibility to model the system’s test behavior, as well as the support for the testing of interconnections, unwrapped cores and user-defined logic. We have implemented our approach and made several experiments on benchmarks as well as industrial designs in order to demonstrate that our approach produces high-quality solution at low computational cost. Index Terms—Scan-chain partitioning, system-on-chip (SOC) testing, test access mechanism design, test data transportation, test scheduling, test solutions. I.

Executing instructions from the cache has been shown to improve the defect coverage of real chips. However, although the faults detected by such tests can be deteremined, there has been no technique to target test generation for an undetected fault. This paper presents a novel technique to map pre-computed test sequences at the module level of a processor, to sequences of instructions. The module level pre-computed test sequence is translated into a temporal logic property and the negation of the property is passed to a bounded model checker. The model checker produces a counter-example for the temporal logic property. This counter-example trace contains the instruction sequence that can be applied at the primary inputs to produce the pre-computed test sequence at the module inputs. This technique has no restrictions on the type of test sequences, so it can be used to map test sequences for any kind of fault to processor instructions. It can also be used in the design phase to produce validation tests. 1

At-speed testing of GHz processors using external testers may not be technically and economically feasible. Hence, there is an emerging need for low-cost, high-quality self-test methodologies, which can be used by processors to test themselves at-speed. Currently, Built-In Self-Test (BIST) is the primary self-test methodology available and is widely used for testing embedded memory cores. In this paper, we report our experiences in applying a commercial BIST methodology to two processor cores and analyze the problems associated with the current hardwarebased BIST methodologies. We propose a new software-based self-testing methodology for processors, which uses a software tester embedded in the processor memory as a vehicle for applying structural tests. The software tester consists of programs for test generation and test application. Prior to the test, structural tests are prepared for processor components in the form of selftest signatures. During the process of self-test, the test generation program expands the self-test signatures into test sets, and the test application program applies the tests to the components-under-test at the speed of the processor. Application of the novel softwarebased self-test method demonstrates its significant cost/fault coverage benefits and its ability to apply at-speed test while alleviating the need for high-speed testers.