Abstract — In this paper, we propose a new methodology for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The wire sizing problem is modeled as an optimization problem formulated as a normal form game and solved using the Nash equilibrium. Game theory allows the optimization of multiple metrics with conflicting objectives. This property is exploited in modeling the wire sizing problem while simultaneously optimizing interconnect delay and crosstalk noise, which are conflicting in nature. The nets connecting the driving cell and the driven cell are divided into net segments. The net segments within a channel are modeled as players, the range of possible wire sizes forms the set of strategies and the payoff function is derived as the geometric mean of interconnect delay and crosstalk noise. The net segments are optimized from the ones closest to the driven cell towards the ones at the driving cell. The complete information about the coupling effects among the nets is extracted after the detailed routing phase. The resulting algorithm for wire sizing is linear in terms of the number of wire segments in the given circuit. Experimental results on several medium and large open core designs indicate that the proposed algorithm yields an average reduction of 21.48 % in interconnect delay and 26.25 % in crosstalk noise over and above the optimization from the Cadence place and route tools without any area overhead. The algorithm performs significantly better than simulated annealing and genetic search as established through experimental results. A mathematical proof of existence for Nash equilibrium solution for the proposed wire sizing formulation is provided. I.

A computationally efficient technique for reducing interconnect active power in VLSI systems is presented. Power reduction is accomplished by simultaneous wire spacing and net ordering, such that cross-capacitances between wires are optimally shared. The existence of a unique poweroptimal wire order within a bundle is proven, and a method to construct this order is derived. The optimal order of wires depends only on the activity factors of the underlying signals; hence, it can be performed prior to spacing optimization. By using this order of wires, optimality of the combined solution is guaranteed (as compared with any other ordering and spacing of the wires). Timing-aware power optimization is enabled by simultaneously considering timing criticality weights and activity factors for the signals. The proposed algorithm has been applied to various interconnect layouts, including wire bundles from high-end microprocessor circuits in 65 nm technology. Interconnect power reduction of 17 % on average has been observed in such bundles.