Abstract approved:

Abstract — A 10b 30MS/s pipelined ADC using fully-differential switched-RC multiplying digital-to-analog converter (MDAC) is presented. It utilizes a resistive loop to reset the feedback capacitor in the MDAC without using the �oating switch. The measured differential and integral nonlinearities of the prototype IC fabricated in a 0.13µm CMOS process are less than 0.54 LSB and 1.75 LSB respectively. The prototype ADC achieves 51.6dB SNDR and 65.9dB SFDR with 1V supply while consuming 17mW power. I.

Abstract—A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented. Using a dual-ADC based approach the digital background scheme is validated with a proof-of-concept prototype fabricated in a 1.8 V 0.18 m CMOS process, where the calibration scheme improves the peak INL of the 45 MS/s ADC from 6.4 LSB to 1.1 LSB after calibration. The SNDR/SFDR is improved from 46.9 dB/48.9 dB to 60.1 dB/70 dB after calibration. Calibration is achieved in approximately 10 4 clock cycles. Index Terms—ADC, analog-to-digital conversion, background, calibration, capacitor mismatch, CMOS, DAC, dual-ADC, missing codes, pipeline, rapid, split-ADC.