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A COMPACT PARALLEL MULTIPLICATION SCHEME BASED ON (7,3) AND (15,4) SELF-TIMED THRESHOLD LOGIC COUNTERS
"... This paper presents a new, a highly compact implementation ofa32 32 parallel multiplier based on parallel counters. The new multiplier is designed using the recently proposed Self-Timed Threshold Logic (STTL). The design is based on a direct multiplication scheme using depth 2 (15,4) and (7,3) STTL ..."
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This paper presents a new, a highly compact implementation ofa32 32 parallel multiplier based on parallel counters. The new multiplier is designed using the recently proposed Self-Timed Threshold Logic (STTL). The design is based on a direct multiplication scheme using depth 2 (15,4) and (7,3) STTL parallel counters and (4:2) compressors. The proposed parallel multiplier reduces the partial product matrix to two rows in only three stages, hence the effective multiplier logic depth is 6. It is shown that the presented scheme significantly reduces the gate count of known proposals for multiplication using threshold logic. 1.
JoséF.López
"... The main result of this paper is the development of a novel, highly compact implementation of the general (m,n)-parallel counter (ie. population counter) based on Self-Timed Threshold Logic (STTL). The presented method is a modification of the Minnick counter. The novel feature of the design is the ..."
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The main result of this paper is the development of a novel, highly compact implementation of the general (m,n)-parallel counter (ie. population counter) based on Self-Timed Threshold Logic (STTL). The presented method is a modification of the Minnick counter. The novel feature of the design is the sharing among all threshold-gates of a single capacitive network for computing the weighted sum of all input bits. Additionally, the differential structure of STTL allows the efficient implementation of the networks of negative weights for layer 1 to layer 2 interconnections. This results in very significant reduction in the number of capacitors and interconnect routing cost and hence total area reduction over other recently reported counter designs. A (7,3) counter is designed using this method. The counter consists of 5 threshold gates arranged in two layers, that is, the resulting circuit has a logic depth of two. Simulation results for the (7,3) counter designed in an industrial 0.25 m process indicate less than 880 W power dissipation operating at 300 MHz. 1.
A COMPACT (M,N) PARALLEL COUNTER CIRCUIT BASED ON SELF TIMED THRESHOLD LOGIC
"... The main result of this paper is the development of a novel, highly compact implementation of the general (m,n)-parallel counter (ie. population counter) based on Self-Timed Threshold Logic (STTL). The presented method is a modification of the Minnick counter. The novel feature of the design is the ..."
Abstract
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The main result of this paper is the development of a novel, highly compact implementation of the general (m,n)-parallel counter (ie. population counter) based on Self-Timed Threshold Logic (STTL). The presented method is a modification of the Minnick counter. The novel feature of the design is the sharing among all threshold-gates of a single capacit-ive network for computing the weighted sum of all input bits. Additionally, the differential structure of STTL al-lows the efficient implementation of the networks of neg-ative weights for layer 1 to layer 2 interconnections. This results in very significant reduction in the number of ca-pacitors and interconnect routing cost and hence total area reduction over other recently reported counter designs. A (7,3) counter is designed using this method. The counter consists of 5 threshold gates arranged in two layers, that is, the resulting circuit has a logic depth of two. Simulation res-ults for the (7,3) counter designed in an industrial 0.25 m process indicate less than 880W power dissipation operat-ing at 300 MHz. 1.
