A technique to reduce the power consumption of the issue logic of superscalar processors is presented. We have evaluated the power consumption of different parts of the architecture through a detailed cycle-by-cycle simulation. The results show that one of the principal power consumption's factor in a superscalar processor is the hardware devoted to extract parallelism from applications. We propose a technique to dynamically resize the instruction queue based on the existing parallelism in different periods of the execution. With the proposed method we can save about 15 per cent on the total power consumption in the processor. 1

In this paper we present our power exploration methodology for data dominated video applications. This formalized methodology is based on the observation that for this type of applications the power consumption is dominated by the memory architecture. Therefore, the first exploration stage is to come up with an optimized memory organisation. Other important observations are that the power consumption of the address generators is of the same magnitude as that of the data-paths and that the address generators are better optimized using specialized techniques.

Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings especially for data-intensive applications. In this paper the effect of the datareuse decisions on the power dissipation but also on area and performance of multimedia applications realized on embedded cores is explored. Experimental results prove that power savings of about 35% can be achieved through the exploitation of data re-use without introducing performance penalties in comparison to reference designs.

A number of code transformations for embedded multimedia applications is presented in this paper and their impact on both system power and performance is evaluated. In terms of power the transformations move the accesses from the large background memories to small buffers that can be kept foreground. This leads to reduction of the memory related power consumption that forms the dominant part of the total power budget of such systems. The transformations also affect the code size and the system's performance which is usually the overriding issue in embedded systems. The impact of the transformations to the performance is analyzed in detail. The code parameters related to the performance of the system and the way they are affected by the transformations are identified. This allows for the development of a systematic methodology for the application of code transformations that achieve an optimal balance between power and performance.

In this paper the three main hardware architectures for the two-dimensional discrete wavelet transform (2D-DWT) are reviewed. Also optimization techniques applicable to all three architectures are described. The main contribution of this work is the quantitative comparison among these design alternatives for the 2D-DWT. The comparison is performed in terms of memory requirements, throughput, and energy dissipation, and is based on a theoretical analysis of the alternative architectures and schedules. Memory requirements, throughput, and energy are expressed by analytical equations with parameters from both the 2D-DWT algorithm and the implementation platform. The parameterized equations enable the early but efficient exploration of the various trade-off related to the selection to the one or the other architecture.

Power management is a low-power technique applicable in almost

This paper describes the impact of our system level data transfer and storage exploration methodology -- as proposed in our mboxATOMIUM approach -- in a software development context on embedded processors. The effectiveness of this methodology on power reduction is demonstrated by optimizing a public domain MPEG-2 video decoder program for an embedded processor. The result is an average factor 3.7 gained on simulated power reduction for the memory transfers. These transfers represent the dominant power consumption source. The presented optimizations can also improve the overall performance of the MPEG-2 algorithm due to the better data caching behaviour. For MPEG-2 additional code transformations were performed to reduce the cycle overhead initially induced by the optimization. 1 Introduction Nowadays, people see the need for a portable multimedia device capable of handling complex and advanced data communication. Text and speech services are already available. But extensions towards ...

This report is divided into two parts which optimize the two video compression standards. But before the video compression standards are optimized is in chapter 2 background information provided on IMEC, power optimization techniques and the power model used in this work. Also area optimization techniques and the area model will be presented there

After its establishment as a new standard for still-image coding, JPEG-2000 is now in the stage of the exploration for efficient implementation in real-life systems. In this paper we focus on the implementation of the frontend part, i.e. the filtering processes performed by the discrete wavelet transform (DWT). The target platforms are programmable processors, since the modern evolution of their design positions them as good alternatives for efficient, flexible and fast time-to-market designs. As a result, to facilitate the incorporation of the new standard in such designs, we present experimental and theoretical results for the data-related cache misses that occur during the DWT, since it has been shown that these consist the main bottleneck in this type of applications. In addition to this, we also rank the presented designs with respect to the power efficiency, under a high-level power estimation scheme. To validate our models, apart from the simulation results, indicative experimental results are presented in superscalar and VLIW real- life architectures.

Low power realization of video applications on embedded cores is described. Code transformations are applied to reduce the data memory power consumption. The transformed code indicates a power efficient data memory architecture while transformations move the main part of memory accesses from larger memories (possibly off-chip) to smaller ones (on-chip). The effect of transformations on performance, which is usually the overriding issue in such systems, is evaluated. It is shown that performance is closely related to program memory power consumption that is in some case orders of magnitude larger than data memory power consumption. The aim of the proposed research is the development of a methodology for the application of data storage and transfer optimizing transformations that achieve a close to optimal balance between power and performance in realizations of multimedia applications on embedded cores. 1.