Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during high-level synthesis (high-level transformations, scheduling and binding). Several techniques pursuing low power are proposed and the potential benefits evaluated. The common idea behind these techniques is to reduce the activity of the functional units (e.g. adders, multipliers) by minimizing the changes of their input operands. Preliminary evaluations obtained from switch-level simulations show that significant improvements can be achieved. 1 Introduction Power consumption can be taken into account at different levels [5]: technological, topological, architectural and algorithmic level. High-level synthesis (HLS) comprises techniques at the architectural and algorithmic level. Traditionally, HLS has been applied to obtain small and fast designs. But little has been done ...

Presented in this paper is a mathematical basis for power-reduction in VLSI systems. This basis is employed to 1.) derive lower bounds on the power dissipation in digital systems and 2.) unify existing power-reduction techniques under a common framework. The proposed basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/sec. Architectures implementing a given algorithm are equivalent to communication networks each with a certain capacity C (also in bits/sec). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. By including various implementation constraints, increasingly realistic lower bounds are calculated. The usefulness of the proposed theory is demonstrated via...

Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resource-binding steps of high-level synthesis. Algorithms for these steps targeting at low-power data-paths and trading off, in some cases, speed and area for low power are presented. The algorithms focus on reducing the activity of the functional units (adders, multipliers) by minimizing the transitions of their input operands. The power consumption of the functional units accounts for a large fraction of the overall data-path power budget. 1 Introduction Current VLSI technology allows circuits with more and more functionality to be integrated in just one chip. Nowadays, portable applications are not only wrist clocks or calculators but multi-media terminals, mobile telephones and other real-time systems. These new applications are based on intensive ...

A novel technique for incorporating the use of dual supply voltages for low power without performance degradation for gate level CMOS VLSI circuits is presented. A formal exact model is developed for the above problem and an efficient near-optimal heuristic is proposed. Power consumption savings up to 25% over and above the best known existing heuristics are demonstrated for combinational circuits in the ISCAS85 benchmark suite. 2 Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages October 9, 1998 Abstract Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply voltage for gates off the critical path it is possible to dramatically reduce power consumption in CMOS VLSI circuits without performance degradation. Interfacing gates operating under multiple supply voltages requires the use of level converters. Due to the non-negligible power c...

This paper deals with power minimization problem for datadominated applications based on a novel concept called partially guarded computation. We divide a functional unit into two parts -- MSP (Most Significant Part) and LSP (Least Significant Part) - and allow the functional unit to perform only the LSP computation if the range of output data can be covered by LSP. We dynamically disable MSP computation to remove unnecessary transitions thereby reducing power consumption. We also propose a systematic approach for determining optimal location of the boundary between the two parts during high-level synthesis. Experimental results show about 10~44% power reduction with about 30~36% area overhead and less than 3% delay overhead in functional units. Keywords Low Power, Partially Guarded Computation 1. Introduction Recently, electronics systems market has proliferated rapidly toward portable computing and communication systems thereby increasing demands for considering low power during ...

Power reductions in VLSI systems have become a critical metric for design evaluation. Although power reduction techniques can be applied at every level of design abstraction, most automated power reduction techniques apply to the lower levels of design abstraction. Previous works have shown that sizable power reductions can be achieved by shutting down a system's sub-circuits when they are not needed. However, these shutdown techniques focus on shutting down only portions of the controller or the datapath of a single custom hardware processor. We therefore investigated the power reduction attainable by the evolving automated technique of functional partitioning, in which a process is automatically divided into multiple simpler, mutually exclusive, communicating processors, and then shut down the inactive processors. By shutting down the entire inactive processor, we have in effect shut down both the controller and datapath. Power reduction is accomplished because only one smaller proce...

this paper, we derive lower and upper bounds on the average signal transition activity via an information-theoretic approach in which symbols generated by a process (possibly correlated) with entropy vae Tl are coded with an average of R bits per symbol. The bounds are asymptotically achievable if the process is stationary and ergodic. We also present a coding algorithm based on the Lempel-Ziv data compression algorithm to achieve the bounds. Bounds are also obtained on the expected num- ber of l's (or O's). These results are applied to, 1.) determine the activity reducing efficiency of different coding algorithms such as Entropy coding, Transition signaling, and Bus-Invert coding, and 2.) determine the lower-bound on the power-delay product given T/ and R. Two examples are provided where transition activity within 4% and 9% of the lower bound is achieved when blocks of 8 symbols and 13 symbols, respectively, are coded at a time

This paper presents (i) a resource constrained scheduling scheme and (ii) a latency-constrained scheduling scheme that minimize power consumption for the case when the resources operate at multiple voltages. The resource-constrained scheduling reduces the power consumption by maximally utilizing resources operating at reduced voltages and at the same time reducing the latency. The latency-constrained scheduling scheme reduces the power consumption by assigning as many nodes (of the data flow graph) as possible to the resources operating at reduced voltages. Two cases have been studied: one in which the possible operating voltages are 5V and 3.3V, and the other in which the operating voltages are 5V, 3.3V and 2.4V. Experiments with some HLS benchmark examples show that the proposed schemes achieve significant power reduction. 1.

OF THE DISSERTATION COMPILER-DIRECTED DYNAMIC VOLTAGE AND FREQUENCY SCALING FOR CPU POWER AND ENERGY REDUCTION by Chung-Hsing Hsu Dissertation Director: Ulrich Kremer The high power consumption of a processor is becoming a critical problem for both battery-powered devices and high-performance computers. It reduces circuit reliability, complicates the cooling technology, shortens the battery lifetime, and increases the production and operation costs of a CPU. One e#ective technique, called dynamic voltage scaling (DVS), achieves CPU power reduction through lowering the CPU supply voltage and clock frequency at runtime. It is e#ective because the CPU power is proportional to the clock frequency and to the square of the supply voltage. However, the CPU power savings come at the cost of degraded performance due to the slower clock frequency. Furthermore, the longer the CPU runs, the more power other computer components (e.g., disk and screen) will consume; not to mention that a user may not be willing to sacrifice any performance. Therefore, DVS should only be applied when it will not noticeably a#ect performance.

Stanford University's Ultra Low Power CMOS project has reported static CMOS circuits operating error-free at supply voltages down to 125mV, and 7-stage 2.0um ring oscillators operating at supply voltages down to 70mV at room temperature at a frequency of 100MHz/V. This paper reports 7-stage 1.5um ring oscillators operating at 170MHz/V at room temperature and 360MHz/V at 77degK at supply voltages down to 27mV. Introduction Professor Allen Peterson's group in Stanford's Space, Telecommunications, and Radioscience Laboratory has been working on an energy efficient CMOS technology since December 1990 which can achieve good performance at extremely low supply voltages [2, 1]. Early theoretical work predicted minimum energy at supply and threshold voltages around 120mV. This was subsequently verified with circuits fabricated at Stanford's Center for Integrated Systems which operated error-free at supply voltages down to 125mV at room temperature [3]. The devices, as fabricated, have threshol...