The introduction of simulation-based analog synthesis tools creates a new challenge for analog modeling. These tools routinely visit 103 to 105 fully simulated circuit solution candidates. What might we do with all this circuit data? We show how to adapt recent ideas from large-scale data mining to build models that capture significant regions of this visited performance space, parametefized by variables manipulated by synthesis, trained by the data points visited during synthesis. Experimental restfits show that we can automatically build useful nonlinear regression models for large analog design spaces.

The use of Support Vector Machines (SVMs) to represent the performance space of analog circuits is explored. In abstract terms, an analog circuit maps a set of input design parameters to a set of performance figures. This function is usually evaluated through simulations and its range defines the feasible performance space of the circuit. In this paper, we directly model performance spaces as mathematical relations. We study approximation approaches based on two-class and one-class SVMs, the latter providing a better tradeoff between accuracy and complexity avoiding "curse of dimensionality" issues with 2-class SVMs. We propose two improvements of the basic one-class SVM performances: conformal mapping and active learning. Finally we develop an efficient algorithm to compute projections, so that topdown methodologies can be easily supported.

Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop.

Analog performance space exploration identifies the range of feasible performance values of a given circuit topology. It is an extremely challenging task of great importance to topology selection and hierarchical sizing. In this paper, a novel technique for the efficient simulation-based exploration of high-dimensional performance spaces is presented. To this end, fundamental circuit design knowledge is described by constraint functions. Based on a linearization of the latter and of the circuit performance functions, a description of the feasible performance range in the form of a polytope is derived. Moreover, the approach is integrated into a hierarchical sizing method, where it propagates topological and technological constraints bottom-up. Practical application results demonstrate the efficiency and usefulness of the new method. 1.

In this paper, we present a hierarchical approach for constraint transformation. The important features of this are: a genetic algorithm (GA) based search engine that computes design parameter ranges, a hierarchically organized characterization mechanism based on the concept of directed intervals that assists the search engine and an analog performance estimator. Experiments were conducted comparing the hierarchical approach with a flat bottom-up one. The results obtained demonstrate the effectiveness of the former approach. Experimental results highlighting the impact of using the characterization information within the constraint transformation process are also presented. 1. Introduction and Motivation Crucial to a top--down mixed--signal design process [12] is a mechanism to propagate the specifications and constraints on the design elements used at one level to those at the next level. This task of transforming the system-level specifications onto component level constraints is c...

Abstract—In this paper, we propose a wavelet collocation method with nonlinear companding to generate behavioral models for analog circuits at the system level. During the overall process of circuit modeling, nonlinear function approximation is an important issue to accurately capture the nonideal input–output relations of analog circuit blocks. While a great number of previous research works focus on the high-dimensional top-down design/synthesis model, which involves large analog design spaces, this paper primarily concentrates on the bottom-up verification model requiring both simple representation and high accuracy. Taking advantage of the local support of wavelet bases, a nonlinear companding method is developed to control the modeling error distribution based on system-level simulation requirements. It, in turn, significantly improves the simulation efficiency at the system level. To demonstrate the promising features of the proposed method, two circuit examples, a fourth-order switched-current filter and a voltage-controlled oscillator, are employed to build the behavioral models. Index Terms—Analog circuits, behavioral modeling, nonlinear companding, wavelet collocation method. I.

A novel methodology is presented to structured yield-- aware synthesis. The trade--off between yield and the unspecified performances is explored along the design space boundaries, while respecting specifications on the other performances. Through the unique combination of multi--objective evolutionary optimization techniques, multi--variate regression modeling and sensitivity--based yield estimation, the designer is given access to this trade--off, all within transistor--level accuracy. Even more, a large reduction in required computer resources is obtained compared to alternative approaches.

analog circuit synthesis. It usually consist of two steps: feasibility design space identification and performance macromodels generation. A feasibility design space is defined as a multidimensional space in which every design satisfies all the design constraints. The minimum set of constraints is the one that ensures the correct functionality of the given circuit topology. Performance macromodels are only constructed and thereby valid in the functionally correct design space. Support vector machines (SVMs) are used as classifier to identify the feasible design space of analog circuits. A kernel is an integral part of the SVM and contributes in obtaining an optimized and accurate classifier. The most commonly used kernels are Radial Basis Function (RBF), polynomial, spline, multilayer perceptron. In this paper, some new kernels and some other kernels composed through modifications on the some of the standard kernels, are explored. The classifiers using these kernel functions have been tested on different analog circuits in order to identify the feasible design space. HSPICE has been used for generation of learning data. Least Square SVM toolbox interfaced with MATLAB was used for classification. We found that use of modified kernels improves classification accuracy as well as shortens classifier generation time.