Analog performance space exploration identifies the range of feasible performance values of a given circuit topology. It is an extremely challenging task of great importance to topology selection and hierarchical sizing. In this paper, a novel technique for the efficient simulation-based exploration of high-dimensional performance spaces is presented. To this end, fundamental circuit design knowledge is described by constraint functions. Based on a linearization of the latter and of the circuit performance functions, a description of the feasible performance range in the form of a polytope is derived. Moreover, the approach is integrated into a hierarchical sizing method, where it propagates topological and technological constraints bottom-up. Practical application results demonstrate the efficiency and usefulness of the new method. 1.

Hierarchy plays a significant role in the design of digital and analog circuits. At each level of the hierarchy it becomes essential to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. This paper proposes a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. A modified simplicial approximation technique is used to generate the feasibility macromodel and a layered volume-slicing methodology with radial basis functions is used to generate the performance macromodel. However, due to lack of space, only details of the performance macromodeling techniques are included. Macromodels are developed and verified for analog blocks at three different levels of hierarchy (current mirror, opamp, and A/D converter). 1. INTRODUCTION As feature sizes shrink even further, an increasing percentage of IC's will have analog circuit designs in them, stressing the need f...

We present an approach for formal verification of the DC and low frequency behavior of synthesized analog designs containing linear components and components whose behavior can be represented by piecewise linear models. A formal model of the structural description of a synthesized design is extracted from the sized component netlist produced by the synthesis tool, in terms of characteristic behavior of the components and various voltage and current laws. For the synthesized implementation to be correct, it must imply a formal model extracted from a user given behavior specification. Circuit implementation and expected behavior are both modeled in the PVS higher-order logic proof checker as linear functions and the PVS decision procedures are used to prove the implication. 1 Introduction The challenges in formally verifying an analog design are some what different from those in verifying digital designs. Analog components exhibit continuous time behavior often represented as an...

A persistent criticism of analog synthesis techniques is that they cannot cope with the complexity of realistic industrial designs, especially system-level designs. We show how recent advances in simulation-based synthesis can be augmented, via appropriate macromodeling, to attack complex analog blocks. To support this claim, we resynthesize from scratch, in several different styles, a complex equalizer/filter block from the frontend of a commercial ADSL CODEC, and verify by full simulation that it matches its original design specifications. As a result, we argue that synthesis has significant potential in both custom and analog IP reuse scenarios.

This paper defines a VHDL-AMS subset for behavioral synthesis of analog systems. The subset includes language constructs for describing most of the functional aspects pertaining to analog systems. Besides, these constructs can be implemented with electronic circuits. Functional aspects, which can be expressed with the subset, relate to two interacting parts. The analog part continuously processes analog signals, while the control part generates control signals for configuring the flow of signals in the analog part. However, some language constructs have to be constrained or augmented, so that they become effective for synthesis. To motivate that constructs in the subset can be synthesized, we present, by means of an example, how VHDL-AMS programs are compiled into an intermediate format. The intermediate format can be either directly mapped to components from a component library, or used for further synthesis-related optimization steps. Finally, we discuss a complete experiment for spe...

During hierarchical design, it becomes essential at each level of the hierarchy to evaluate if a sub-block design is feasible and if so which design style is the best candidate for the particular problem. We propose a general methodology for evaluating the feasibility and the performance of sub-blocks at all levels of the hierarchy. In this paper we concentrate on techniques to model the feasibility region. The methodology is general and can be used for both analog and digital circuits. Macromodels are developed and verified for analog blocks at different levels of hierarchy. 1 Hierarchical Circuit Design An increasing percentage of IC's have analog circuit designs in them. These and other requirements stress the need for automatic synthesis tools for analog circuits. Hierarchy plays a significant role in the design of digital and analog circuits. A large design can be broken up into smaller sub-blocks at the different levels of a hierarchy. An example hierarchy for an A/D converter ...

Abstract—This paper presents an implementation of a decoupled optimization technique for design of switching regulators using genetic algorithms (GAs). The optimization process entails the selection of component values in a switching regulator, in order to meet the static and dynamic requirements. Although the proposed method inherits characteristics of evolutionary computations that involve randomness, recombination, and survival of the fittest, it does not perform a whole-circuit optimization. Thus, intensive computations that are usually found in stochastic optimization techniques can be avoided. Similar to many design approaches for power electronics circuits, a regulator is decoupled into two components, namely the power conversion stage (PCS) and the feedback network (FN). The PCS is optimized with the required static characteristics, whilst the FN is optimized with the required static and dynamic behaviors of the whole system. Systematic optimization procedures will be described and the technique is illustrated with the design of a buck regulator with overcurrent protection. The predicted results are compared with the published results available in the literature and are verified with experimental measurements. Index Terms—Circuit optimization, circuit simulation, computer-aided design, genetic algorithms, power electronics. I.

This dissertation concerns the principles and techniques for scalable evolutionary computation to achieve better solutions for larger problems with more computational resources. It suggests that many of the limitations of existent evolutionary algorithms, such as premature convergence, stagnation, loss of diversity, lack of reliability and efficiency, are derived from the fundamental convergent evolution model, the oversimplified “survival of the fittest” Darwinian evolution model. Within this model, the higher the fitness the population achieves, the more the search capability is lost. This is also the case for many other conventional search techniques. The main result of this dissertation is the introduction of a novel sustainable evolution model, the Hierarchical Fair Competition (HFC) model, and corresponding five sustainable evolutionary algorithms (EA) for evolutionary search. By maintaining individuals in hierarchically organized fitness levels and keeping evolution going at all fitness levels, HFC transforms the conventional convergent evolutionary computation model into a sustainable search framework by ensuring a continuous supply and incorporation of low-level building blocks and by culturing and maintaining building blocks of intermediate levels with its

This paper presents a top-down design methodology to synthesize mixed-signal systems described at behavioral level. Our methodology is intended to automate the synthesis process of analog CMOS integrated circuits. Also, the method enables the circuit description at high level of abstraction where complex systems are easier to specify. The behavioral models are represented by a set of simultaneous differential and algebraic equations (DAEs), which are written in VHDL-AMS using simple simultaneous and procedural statements. We present an algorithm to perform the topology selection process. As an example, a Dual-Tone Multiple-Frequency decoder is synthesized from behavioral model to analog CMOS transistor level. 1 Introduction The emerging analog hardware description languages will speed up the analog verification process and enable the analog designer to describe circuits at higher levels of abstraction. Analog integrated circuits have been typically designed at circuit, component and ...

This paper presents an analog circuit design assistance tool called Adapt. The tool can perform automatic circuit sizing over a wide range of heterogeneous design parameters. We present Adapt's architecture and the design flow, discuss important user-interface aspects of the tool, disclose details on the optimization algorithms incorporated in the tool, and demonstrate the practical strength of the tool. The industrial-strength capabilities of the tool are showcased using an RF low-noise amplifier that is used in Bluetooth applications.