We address the problem of instruction selection in code generation for embedded digital signal processors. Recent work has shown that this task can be efficiently solved by tree covering with dynamic programming, even in combination with the task of register allocation. However, performing instruction selection by tree-covering only does not exploit available instruction-level parallelism, for instance in form of multiply-accumulate instructions or parallel data moves. In this paper we investigate how such complex instructions may affect detection of optimal treecovers, and we present a two-phase scheme for instruction selection which exploits available instruction-level parallelism. At the expense of higher compilation time, this technique may significantly increase the code quality compared to previous work, which is demonstrated for a widespread DSP.

Code generation for embedded special-purpose processors is usually a difficult task for compiler writers as well as for assembly language programmers. This report describes an experimental demonstration prototype of a code generation tool. The tool is a retargetable assembly-code-level macro expander capable of program flow analysis. The main advantage offered by this macro expander is its strong support for macro hierarchy. The enhanced modularity provided by hierarchical macro libraries can make the code (produced either by the compiler writer or by the assembly language programmer) more easily readable, maintainable, and reusable. Still, a procedure written in the macro language retains its machine-specificity and, consequently, its efficiency.