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25
Verification of Pipeline Circuits
 In ACL2 Workshop 2000 (proceedings are available as UTCS
, 2000
"... The use of pipelines is an important technique in contemporary hardware design, particularly at the level of registertransfer logic (RTL). Earlier formal analysis (e.g., [4]) using the ACL2 theorem prover showed correctness of pipelined floatingpoint RTL. This paper extends that work by consid ..."
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The use of pipelines is an important technique in contemporary hardware design, particularly at the level of registertransfer logic (RTL). Earlier formal analysis (e.g., [4]) using the ACL2 theorem prover showed correctness of pipelined floatingpoint RTL. This paper extends that work by considering a notion of a conditional pipeline, essentially the result of sharing hardware among several distinct pipelines. We have employed a pipeline tool, written in ACL2 but completely unverified, to find a pipelinerelated bug in an industrial hardware design, which has since been corrected.
Floatingpoint verification
 International Journal Of ManMachine Studies
, 1995
"... Abstract: This paper overviews the application of formal verification techniques to hardware in general, and to floatingpoint hardware in particular. A specific challenge is to connect the usual mathematical view of continuous arithmetic operations with the discrete world, in a credible and verifia ..."
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Abstract: This paper overviews the application of formal verification techniques to hardware in general, and to floatingpoint hardware in particular. A specific challenge is to connect the usual mathematical view of continuous arithmetic operations with the discrete world, in a credible and verifiable way.
Formal Verification of Microprocessors at AMD
, 2002
"... Formal Verification History We have emphasized automated theorem proving. 199596: Division and square root algorithms for AMDK5 microcode[3, 5] 1997present: Proofs of floatingpoint algorithms and actual RTL that use ACL2 on the AMD Athlon processor and its derivatives [6, 7, 8] \Gamma ..."
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Formal Verification History We have emphasized automated theorem proving. 199596: Division and square root algorithms for AMDK5 microcode[3, 5] 1997present: Proofs of floatingpoint algorithms and actual RTL that use ACL2 on the AMD Athlon processor and its derivatives [6, 7, 8] \Gamma We have a translator from our proprietary RTL to ACL2 [7] that enables RTL proofs. 2001: Completed some protocollevel proofs 5 A natural target for theorem provers [10, 4] Concise formal specifications relating outputs to inputs The RTL is relatively tractable. \Gamma While the size of an FPU may be substantial, the logic tends to decompose by operation. \Gamma The interfaces with other modules are smaller and simpler. Complexity of floatingpoint designs causes problems for other verification approaches. \Gamma Testing alone may be inadequate. \Gamma Decision procedures used in formal verification traditionally have capacity limitations, for example for multiplication and shiftin
Behavioral Properties of FloatingPoint Programs ⋆
"... Abstract. We propose an expressive language to specify formally behavioral properties of programs involving floatingpoint computations. We present a deductive verification technique, which allows to prove formally that a given program meets its specifications, using either SMTclass automatic theor ..."
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Abstract. We propose an expressive language to specify formally behavioral properties of programs involving floatingpoint computations. We present a deductive verification technique, which allows to prove formally that a given program meets its specifications, using either SMTclass automatic theorem provers or general interactive proof assistants. Experiments using the FramaC platform for static analysis of C code are presented. 1
A mechanized program verifier
 In IFIP Working Conference on the Program Verifier Challenge
, 2005
"... Abstract. In my view, the “verification problem ” is the theorem proving problem, restricted to a computational logic. My approach is: adopt a functional programming language, build a general purpose formal reasoning engine around it, integrate it into a program and proof development environment, an ..."
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Abstract. In my view, the “verification problem ” is the theorem proving problem, restricted to a computational logic. My approach is: adopt a functional programming language, build a general purpose formal reasoning engine around it, integrate it into a program and proof development environment, and apply it to model and verify a wide variety of computing artifacts, usually modeled operationally within the functional programming language. Everything done in this approach is software verification since the models are runnable programs in a subset of an ANSI standard programming language (Common Lisp). But this approach is of interest to proponents of other approaches (e.g., verification of procedural programs or synthesis) because of the nature of the mathematics of computing. I summarize the progress so far using this approach, sketch the key research challenges ahead and describe my vision of the role and shape of a useful verification system. 1
An ACL2 Proof of Write Invalidate Cache Coherence
 In Proc. CAV'98, volume 1427 of LNCS
, 1998
"... . As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its own local cache, interact with a global memory via a bus which is snooped by the caches. 1 Ongoing Industrial Applica ..."
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. As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its own local cache, interact with a global memory via a bus which is snooped by the caches. 1 Ongoing Industrial Applications of ACL2 The ACL2 theorem proving system is finding use in industrialscale verification projects. Two significant projects which have been reported previously are  the mechanical verification of the floatingpoint division microcode for the AMDK5 TM [6], and  the ACL2 modeling of the Motorola CAP digital signal processor and its use to prove that a pipeline hazard detection predicate was correct and that several DSP microcode applications were correct [1]. The abstract of a recent talk given by David Russinoff of Advanced Micro Devices, Inc., summarizes the current AMD work with ACL2: Formal design verification at AMD has focused on the elementary arithmetic floating point op...
A Transformational Perspective into the Core of an Abstract Class Loader for the SSP
 ACM Trans. on Embedded Computing Sys
"... The SSP is a hardware implementation of a subset of the JVM for use in high consequence embedded applications. In this context, a majority of the activities belonging to class loading, as it is defined in the specification of the JVM, can be performed statically. Static class loading has the net res ..."
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The SSP is a hardware implementation of a subset of the JVM for use in high consequence embedded applications. In this context, a majority of the activities belonging to class loading, as it is defined in the specification of the JVM, can be performed statically. Static class loading has the net result of dramatically simplifying the design of the SSP as well as increasing its performance. The functionality of the class loader can be implemented using strategic programming techniques. The incremental nature of strategic programming is amenable to formal verification. This article gives an overview of the core class loading activities for the SSP, their implementation in the strategic programming language TL, and outlines the approach to formal verification of the implementation. 1
Integrating CCG analysis into ACL2
 In Eighth International Workshop on Termination, August 2006. Part of FLOC ’06
"... ACL2 [6–8] is a powerful, industrial strength theorem proving system, which has been used on ..."
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ACL2 [6–8] is a powerful, industrial strength theorem proving system, which has been used on
Formal Verification of FloatingPoint RTL at AMD Using the ACL2 Theorem Prover
"... Abstract We describe a methodology for the formal verification of the correctness, including IEEEcompliance, of registertransfer level models of floatingpoint hardware designs, and its application to the floatingpoint units of a series of commercial microprocessors produced by Advanced Micro De ..."
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Abstract We describe a methodology for the formal verification of the correctness, including IEEEcompliance, of registertransfer level models of floatingpoint hardware designs, and its application to the floatingpoint units of a series of commercial microprocessors produced by Advanced Micro Devices, Inc. The methodology is based on a mechanical translator from a synthesizable subset of the Verilog hardware description language, in which the models are coded, to the formal logic of the ACL2 theorem prover. Behavioral specifications of correctness, coded in essentially the same language as the designs, are translated as well, and ultimately checked with the ACL2 prover. Keywords — Formal verification, Floatingpoint arithmetic, IEEEcompliance, Theorem proving, ACL2
A LightWeight Framework for Hardware Verification
 In TACAS'99
, 1999
"... This paper describes a deductive verification framework that allows the use of general purpose decision procedures and traditional model checking along with domain specific inference rules. The latter allow established algorithms for timing verification and other hardware verification tasks to b ..."
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This paper describes a deductive verification framework that allows the use of general purpose decision procedures and traditional model checking along with domain specific inference rules. The latter allow established algorithms for timing verification and other hardware verification tasks to be imported into the verification framework. To demonstrate this approach, a SRT divider is verified using a transistorlevel model with timing.