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29
Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters
, 2000
"... Pipelined analogtodigital converters (ADCs) tend to be sensitive to component mismatches in their internal digitaltoanalog converters (DACs). The component mismatches give rise to error, referred to as DAC noise, which is not attenuated or cancelled along the pipeline as are other types of noise. ..."
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Cited by 21 (4 self)
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Pipelined analogtodigital converters (ADCs) tend to be sensitive to component mismatches in their internal digitaltoanalog converters (DACs). The component mismatches give rise to error, referred to as DAC noise, which is not attenuated or cancelled along the pipeline as are other types of noise. This paper describes an alldigital technique that significantly mitigates this problem. The technique continuously measures and cancels the portion of the ADC error arising from DAC noise during normal operation of the ADC, so no special calibration signal or autocalibration phase is required. The details of the technique are described in the context of a nominal 14bit pipelined ADC example at both the signal processing and register transfer levels. Through this example, the paper demonstrates that in the presence of realistic component matching limitations the technique can improve the overall ADC accuracy by several bits with only moderate digital hardware complexity. I. INTRODUCTION ...
A 3.3V SinglePoly CMOS Audio ADC DeltaSigma Modulator with 98dB Peak SINAD and 105dB Peak SFDR
 IEEE J. SolidState Circuits
, 2000
"... This paper presents a secondorder ## modulator for audioband A#D conversion implemented in a 3.3V, 0.5#m, singlepoly CMOS process using metalmetal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a lowcomplexity #rstorder mismatchshaping 33level DAC and a 33leve ..."
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Cited by 18 (13 self)
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This paper presents a secondorder ## modulator for audioband A#D conversion implemented in a 3.3V, 0.5#m, singlepoly CMOS process using metalmetal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a lowcomplexity #rstorder mismatchshaping 33level DAC and a 33level #ash ADC with digital commonmode rejection and dynamic element matching of comparator o#sets. These signal processing innovations, combined with established circuit techniques, enable state of the art performance in CMOS technology optimized for digital circuits. I. Introduction For mixedsignal ICs with high digital circuit content, singlepoly CMOS optimized for digital circuits can provide the lowest overall implementation cost. For example, it is preferable to avoid the expense of doublepoly capacitors, thickoxide transistors for 5V operation, or other analog process enhancements when analog circuits such as data converters make up only a small portion of the total die area. This ...
A 12mW ADC DeltaSigma Modulator with 80 dB of Dynamic Range Integrated in a SingleChip Bluetooth Transceiver
, 2002
"... This paper presents a switchedcapacitor multibit ADC deltasigma modulator for baseband demodulation integrated in a singlechip Bluetooth radiomodem transceiver that achieves 77 dB of signaltonoiseplusdistortion ratio (SINAD) and 80 dB of dynamic range over a 500kHz bandwidth with a 32MHz ..."
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Cited by 11 (6 self)
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This paper presents a switchedcapacitor multibit ADC deltasigma modulator for baseband demodulation integrated in a singlechip Bluetooth radiomodem transceiver that achieves 77 dB of signaltonoiseplusdistortion ratio (SINAD) and 80 dB of dynamic range over a 500kHz bandwidth with a 32MHz sample rate. The 1mm 2 circuit is implemented in a 0.35 m BiCMOS SOI process and consumes 4.4 mA of current from a 2.7V supply.
Digital Background Correction of Harmonic Distortion in Pipelined ADCs
 Circuits and System I: Regular Papers, IEEE Transactions on
, 2006
"... Abstract—Pipelined analogtodigital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dom ..."
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Cited by 11 (3 self)
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Abstract—Pipelined analogtodigital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in highresolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers. It allows the use of higher distortion and, therefore, lower power residue amplifiers in highaccuracy pipelined ADCs, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs. Index Terms—Analogtodigital conversion, calibration, harmonic distortion, mixed analog–digital integrated circuits (ICs).
An Audio ADC DeltaSigma Modulator with 100dB Peak SINAD and 102dB DR Using a SecondOrder MismatchShaping DAC
 IEEE J. Solid State Circuits
, 2001
"... A secondorder audio analogtodigital converter (ADC) 16 modulator using a secondorder 33level treestructured mismatchshaping digitaltoanalog converter (DAC) is presented. Key logic simplifications in the design of the mismatch shaping DAC encoder are shown which yield the lowest complexit ..."
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Cited by 9 (4 self)
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A secondorder audio analogtodigital converter (ADC) 16 modulator using a secondorder 33level treestructured mismatchshaping digitaltoanalog converter (DAC) is presented. Key logic simplifications in the design of the mismatch shaping DAC encoder are shown which yield the lowest complexity secondorder mismatchshaping DAC known to the authors. The phenomenon of signaldependent DAC noise modulation in mismatchshaping DACs is illustrated, and a modified secondorder inputlayer switching block is presented which reduces inband DAC noise modulation by 6 dB. Implementation details and measured performance of the 3.3V 0.5 m singlepoly CMOS prototype are presented. All 12 prototype devices achieve better than 100dB signaltonoiseanddistortion and 102dB dynamic range over a 1020 kHz measurement bandwidth. Index Termsanalogdigital conversion, CMOS analog integrated circuits, deltasigma modulation, digitalanalog conversion, dynamic element matching, mixed analogdigital integrated circuits. I.
Simplified Logic for FirstOrder and SecondOrder MismatchShaping DigitaltoAnalog Converters
 AND GALTON: NECESSARY AND SUFFICIENT CONDITIONS FOR MISMATCH SHAPING 759
, 2001
"... Mismatchshaping digitaltoanalog converters (DACs) have become widely used in highperformance deltasigma data converters because they facilitate deltasigma modulators with multibit quantization. Relative to singlebit quantization, multibit quantization significantly relaxes the analog circuit ..."
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Cited by 8 (5 self)
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Mismatchshaping digitaltoanalog converters (DACs) have become widely used in highperformance deltasigma data converters because they facilitate deltasigma modulators with multibit quantization. Relative to singlebit quantization, multibit quantization significantly relaxes the analog circuit performance necessary to achieve a given level of data converter precision, but significant digital logic is required to perform the mismatch shaping. In modern very large scale integration processes optimized for digital circuitry, this tends to be a good tradeoff in terms of both area and power consumption. It is nonetheless desirable to minimize the digital complexity as much as possible. Moreover, in deltasigma analogtodigital converters the mismatchshaping logic is in the feedback path of the deltasigma modulator, so it is essential to maintain a sufficiently small propagation delay through the mismatchshaping logic. This paper presents and analyzes several variations of the switching blocks within a treestructured mismatchshaping DAC that result in the most hardwareefficient firstorder and secondorder mismatch shaping DAC implementations yet known to the authors. The variations presented allow designers to tradeoff complexity for propagationdelay reduction so as to tailor designs to specific applications.
A digitally enhanced 1.8V 15bit 40MSample/s CMOS pipelined ADC
 Univ of Calif Los Angeles. Downloaded on November 5, 2009 at 13:59 from IEEE Xplore. Restrictions apply. IEEE JOURNAL OF SOLIDSTATE CIRCUITS, VOL
, 2004
"... analogtodigital converter with 90dB spuriousfree dynamic range (SFDR) and 72dB peak signaltonoise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is ..."
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Cited by 8 (0 self)
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analogtodigital converter with 90dB spuriousfree dynamic range (SFDR) and 72dB peak signaltonoise ratio (SNR) over the full Nyquist band is presented. Its differential and integral nonlinearities are 0.25 LSB and 1.5 LSB, respectively, and its power consumption is 400 mW. This performance is enabled by digital background calibration of internal digitaltoanalog converter (DAC) noise and interstage gain errors. The calibration achieves improvements of better than 12 dB in signaltonoise plus distortion ratio and 20 dB in SFDR relative to the case where calibration is disabled. Other enabling features of the prototype integrated circuit (IC) include a lowlatency, segmented, dynamic elementmatching DAC, distributed passive input signal sampling, and asymmetric clocking to maximize the time available for the firststage residue amplifier to settle. The IC is realized in a 0.18 m mixedsignal CMOS process and has a die size of 4mm 5 mm. Index Terms—Analogtodigital conversion, calibration, mixed analog–digital integrated circuits (ICs).
Necessary and Sufficient Conditions for Mismatch Shaping in a General Class of Multibit Dacs
, 2002
"... Multibit digitaltoanalog converters (DACs) are often constructed by combining several 1bit DACs of equal or different weights in parallel. In such DACs, component mismatches give rise to signal dependent error that can be viewed as additive DAC noise. In some cases these DACs use dynamic element ..."
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Cited by 7 (4 self)
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Multibit digitaltoanalog converters (DACs) are often constructed by combining several 1bit DACs of equal or different weights in parallel. In such DACs, component mismatches give rise to signal dependent error that can be viewed as additive DAC noise. In some cases these DACs use dynamic element matching techniques to decorrelate the DAC mismatch noise from the input sequence and suppress its power in certain frequency bands. Such DACs are referred to as mismatchshaping DACs and have been used widely as enabling components in stateoftheart data converters. Several different mismatchshaping DAC topologies have been presented, but theoretical analyses have been scarce and no general unifying theory has been presented in the previously published literature. This paper presents such a unifying theory in the form of necessary and sufficient conditions for a multibit DAC to be a mismatchshaping DAC and applies the conditions to evaluate the DAC noise generated by several of the previously published mismatchshaping DACs and qualitatively compare their behavior.
A study of dynamic element matching techniques for threelevel unit elements
 IEEE Trans. Circuits Syst. II
, 2000
"... Abstract—Highly linear 3level unit elements are available in any fully differential circuit. This is because each unit element in such a circuit can be either positively selected, negatively selected, or not selected. This paper presents a study of dynamic element techniques for such elements. It i ..."
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Cited by 5 (4 self)
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Abstract—Highly linear 3level unit elements are available in any fully differential circuit. This is because each unit element in such a circuit can be either positively selected, negatively selected, or not selected. This paper presents a study of dynamic element techniques for such elements. It is shown how traditional dynamic elementmatching techniques for 2level unit elements such as the data directed swapper, the vector selector, and the tree structure can be adapted toward linear 3level elements. In all these cases, the amount of hardware is reduced significantly by using 3level elements. Also several efficient “data weighted averaging”like implementations are presented. Then the effect of the nonlinearity of the 3level unit element is analyzed. It is shown that this gives an additional error contribution that may limit the performance. Therefore, several efficient techniques to shape this effect as well are introduced. Index Terms—Analogtodigital, digitaltoanalog, dynamic elementmatching, spectral shaping.
An approach to tackle quantization noise folding in doublesampling 61 modulation A/D converters
 IEEE Trans. Circuits Syst. II
, 2003
"... Abstract—61modulation is a proven method to realize high and very highresolution analogtodigital converters. A particularly efficient way to implement such a modulator uses doublesampling where the circuit operates during both clock phases of the masterclock. Hence, the sampling frequency is ..."
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Cited by 5 (4 self)
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Abstract—61modulation is a proven method to realize high and very highresolution analogtodigital converters. A particularly efficient way to implement such a modulator uses doublesampling where the circuit operates during both clock phases of the masterclock. Hence, the sampling frequency is twice the masterclock frequency. Unfortunately, path mismatch between both sampling branches causes a part of the quantization noise to fold from the Nyquist frequency back in the signal band. Therefore, the performance is severely degraded. In this paper, we show that the problem is reduced but not eliminated by employing multibit quantization. Next, we present an indepth solution for the problem. The approach consists of modifying the quantization noise transfer function of the overall modulator to have one or several zeros at the Nyquist frequency. This way the effect of noise folding can nearly be eliminated. It is shown that this can be implemented by a simple modification of one of the integrators of the overall modulator circuit. Finally, several design examples of singlebit and multibit modulators are discussed. Index Terms—Analogtodigital conversion, doublesampling, spectral shaping.