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Theory of latencyinsensitive design
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 2001
"... The theory of latencyinsensitive design is presented as the foundation of a new correctbyconstruction methodology to design complex systems by assembling intellectual property components. Latencyinsensitive designs are synchronous distributed systems and are realized by composing functional mod ..."
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Cited by 125 (15 self)
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The theory of latencyinsensitive design is presented as the foundation of a new correctbyconstruction methodology to design complex systems by assembling intellectual property components. Latencyinsensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The goal of the protocol is to guarantee that latencyinsensitive designs composed of functionally correct modules behave correctly independently of the channel latencies. This allows us to increase the robustness of a design implementation because any delay variations of a channel can be “recovered ” by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latencyinsensitive methodology to design large digital integrated circuits by using deep submicrometer technologies.
Synthesis of Timed Asynchronous Circuits
 IEEE Transactions on VLSI Systems
, 1993
"... In this paper we present a synthesis method that utilizes timing constraints to generate timed asynchronous circuits. By unfolding the cyclic graph specification of an asynchronous circuit into an infinite acyclic graph, we are able to use efficient algorithms to analyze the given timing constraints ..."
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Cited by 87 (16 self)
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In this paper we present a synthesis method that utilizes timing constraints to generate timed asynchronous circuits. By unfolding the cyclic graph specification of an asynchronous circuit into an infinite acyclic graph, we are able to use efficient algorithms to analyze the given timing constraints. We derive a sufficient condition for the removal of redundancy in the specification. Based on this condition, we only need to analyze a finite subgraph of the infinite acyclic graph for derivation of a correct implementation. To the reduced specification, we apply a systematic synthesis procedure that further optimizes the implementation based on the timing constraints. Using realistic circuit examples, we demonstrate that the resulting timed implementation can be significantly reduced in complexity from its speedindependent counterpart while remaining hazardfree under the given timing constraints.
Automatic synthesis of burstmode asynchronous controllers
, 1995
"... Asynchronous design has enjoyed a revival of interest recently, as designers seek to eliminate penalties of traditional synchronous design. In principle, asynchronous methods promise to avoid overhead due to clock skew, worstcase design assumptions and resynchronization of asynchronous external inp ..."
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Cited by 75 (10 self)
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Asynchronous design has enjoyed a revival of interest recently, as designers seek to eliminate penalties of traditional synchronous design. In principle, asynchronous methods promise to avoid overhead due to clock skew, worstcase design assumptions and resynchronization of asynchronous external inputs. In practice, however, many asynchronous design methods suffer from a number of problems: unsound algorithms (implementations may have hazards), harsh restrictions on the range of designs that can be handled (singleinput changes only), incompatibility with existing design styles and inefficiency in the resulting circuits. This thesis presents a new locallyclocked design method for the synthesis of asynchronous controllers. The method has been automated, is proven correct and produces highperformance implementations which are hazardfree at the gatelevel. Implementations allow multipleinput changes and handle a relatively unconstrained class of behaviors (called "burstmode" specifications). The method produces statemachine implementations with a minimal or nearminimal number of states. Implementations can be easily built in such common VLSI design styles as gatearray, standard cell and fullcustom. Realizations typically have the latency of
Faster Maximum and Minimum Mean Cycle Algorithms for System Performance Analysis
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
, 1997
"... Maximum and minimum mean cycle problems are important problems with many applications in performance analysis of synchronous and asynchronous digital systems including rate analysis of embedded systems, in discreteevent systems, and in graph theory. Karp's algorithm is one of the fastest and c ..."
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Cited by 68 (4 self)
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Maximum and minimum mean cycle problems are important problems with many applications in performance analysis of synchronous and asynchronous digital systems including rate analysis of embedded systems, in discreteevent systems, and in graph theory. Karp's algorithm is one of the fastest and commonest algorithms for both of these problems. We present this paper mainly in the context of the maximum mean cycle problem. We show that Karp's algorithm processes more vertices and arcs than needed to find the maximum cycle mean of a digraph. This observation motivated us to propose a new graph unfolding scheme that remedies this deficiency and leads to three faster algorithms with different characteristics. Asymptotic analysis tells us that our algorithms always run faster than Karp's algorithm. Experiments on benchmark graphs confirm this fact for most of the graphs. Like Karp's algorithm, they are also applicable to both the maximum and minimum mean cycle problems. Moreover, one of them is...
An introduction to asynchronous circuit design
 THE ENCYCLOPEDIA OF COMPUTER SCIENCE AND TECHNOLOGY
, 1997
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A Methodology for CorrectbyConstruction Latency Insensitive Design
 IN PROC. INTL. CONF. ON COMPUTERAIDED DESIGN
, 2003
"... In Deep SubMicron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the design functionally insensitive to the latency of long wires. Given a synchronous specification of a design, we generate a ..."
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Cited by 60 (13 self)
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In Deep SubMicron (DSM) designs, performance will depend critically on the latency of long wires. We propose a new synthesis methodology for synchronous systems that makes the design functionally insensitive to the latency of long wires. Given a synchronous specification of a design, we generate a functionally equivalent synchronous implementation that can tolerate arbitrary communication latency between latches. By using latches we can break a long wire in short segments which can be traversed while meeting a single clock cycle constraint. The overall goal is to obtain a design that is robust with respect to delays of long wires, in a shorter time by reducing the multiple iterations between logical and physical design, and with performance that is optimized with respect to the speed of the single components of the design. In this paper we describe the details of the proposed methodology as well as report on the latency insensitive design of PDLX , an outoforder microprocessor with speculativeexecution.
Automatic synthesis of extended burstmode circuits: part II (automatic synthesis)
 IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN
, 1999
"... We introduce a new design style called extended burstmode. The extended burstmode design style covers a wide spectrum of sequential circuits ranging from delayinsensitive to synchronous. We can synthesize multipleinput change asynchronous finite state machines, and many circuits that fall in the ..."
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Cited by 51 (12 self)
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We introduce a new design style called extended burstmode. The extended burstmode design style covers a wide spectrum of sequential circuits ranging from delayinsensitive to synchronous. We can synthesize multipleinput change asynchronous finite state machines, and many circuits that fall in the gray area (hard to classify as synchronous or asynchronous) which are difficult or impossible to synthesize automatically using existing methods. Our implementation of extended burstmode machines uses standard CMOS logic, generates lowlatency outputs, and guarantees freedom from hazards at the gate level. In Part II, we present a complete set of automated sequential synthesis algorithms: hazardfree state assignment, hazardfree state minimization, and criticalracefree state encoding. Experimental data from a large set of examples are presented and compared to competing methods, whenever possible.
An algorithm for exact bounds on the time separation of events in concurrent systems
 IEEE Transactions on Computers
, 1995
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ComputerAided Synthesis And Verification Of GateLevel Timed Circuits
, 1995
"... In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to processing and environmental variations, provide component modularity, and lower system power requirement ..."
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Cited by 48 (21 self)
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In recent years, there has been a resurgence of interest in the design of asynchronous circuits due to their ability to eliminate clock skew problems, achieve average case performance, adapt to processing and environmental variations, provide component modularity, and lower system power requirements. Traditional academic asynchronous designs methods use unbounded delay assumptions, resulting in circuits that are verifiable, but ignore timing for simplicity, leading to unnecessarily conservative designs. In industry, however, timing is critical to reduce both chip area and circuit delay. Due to a lack of formal methods that handle timing information correctly, circuits with timing constraints usually require extensive simulation to gain confidence in the design. This thesis bridges this gap by introducing timed circuits in which explicit timing information is incorporated into the specification and utilized throughout the design procedure to optimize the implementation. Our timed circu...