As very large scale integrated (VLSI) circuits move into the era of deepsubmicron (DSM) technology and gigahertz frequency, the system performance has increasingly become dominated by the interconnect delay. This dissertation presents five related research topics on interconnect layout optimization, and interconnect extraction and modeling: the multi-source wire sizing (MSWS) problem, the simultaneous transistor and interconnect sizing (STIS) problem, the global interconnect sizing and spacing (GISS) problem, the interconnect capacitance extraction problem, and the interconnect inductance extraction problems. Given a routing tree with multiple sources, the MSWS problem determines the optimal widths of the wire segments such that the delay is minimized. We reveal several interesting properties for the optimal MSWS solution, of which the most important is the bundled refinement property. Based on this property, we propose a polynomial time algorithm, which uses iterative bundled refinement operations to compute lower and upper bounds of an optimal solution. Since the algorithm often achieves identical lower and upper bounds in experiments, the optimal solution is obtained simply by the bound computation. Furthermore, this algorithm can be used for single-source wire sizing problem and runs 100x xxi faster than previous methods. It has replaced previous single-source wire sizing methods in practice.

A wide variety of nonlinear convex optimization problems can be cast as problems involving linear matrix inequalities (LMIs), and hence efficiently solved using recently developed interior-point methods. In this paper, we will consider two classes of optimization problems with LMI constraints: ffl The semidefinite programming problem, i.e., the problem of minimizing a linear function subject to a linear matrix inequality. Semidefinite programming is an important numerical tool for analysis and synthesis in systems and control theory. It has also been recognized in combinatorial optimization as a valuable technique for obtaining bounds on the solution of NP-hard problems.

We consider mixed semidenite{quadratic{linear programs. These are linear optimization problems with three kinds of cone constraints, namely: the semidenite cone, the quadratic cone and the nonnegative orthant. We outline a primal{dual path following method to solve these problems and highlight the main features of SDPpack, a Matlab package which solves such programs. We give some examples where such mixed programs arise, and provide numerical results on benchmark problems. 1 Introduction We consider the following mixed semidenite{quadratic{linear program (SQLP): max b T y (1) s:t: F (k) 0 + P m i=1 y i F (k) i 0; k = 1; : : : ; L (2) k(c (k) A (k) ) T yk (k) (g (k) ) T y; k = 1; : : : ; M (3) (A (0) ) T y c (0) (4) where y 2 R m and F (k) i 2 S nk ; i = 0; : : : ; m; k = 1; : : : ; L A (k) 2 R mpk ; c (k) 2 R pk ; g (k) 2 R m ; (k) 2 R; k = 1; : : : ; M A (0) 2 R mp0 ; c (0) 2 R p0 : The rst set of constraints (2)...

Abstract — New back-end design for manufacturability rules have brought guarantee rules for interconnect matching. These rules indicate a certain capacitance matching guarantee given spacing between interconnects and interconnect area. Yet, the number of these rules is so few that they are of limited value in circuit or interconnect optimization. A method to infer additional guarantees from the provided guarantees is necessary so that optimization can be optimal. In this paper, we target two problems. First, we present a methodology to infer additional matching guarantees through extracting correlation information from the given limited set of matching guarantees in the design manual. In order to achieve this, we propose a multi-function variant of multi-variate Newton-Raphson method to extract parameters of the proposed dimension- and distancebased process correlation model for interconnects. We propose to use the extracted correlation information to infer a continuum of matching rules through simulation with proposed modifications to the standard capacitance extraction procedure. Secondly, we show how to directly incorporate the inferred interconnect matching guarantees for accurate interconnect optimization in a flexible geometric programming construction. We show how much resource savings are possible through inferring of new matching rules. Applying the inferred mismatch guarantees allows a geometric programming-based H-tree optimization to reduce the clock tree resources 27 % on average and up to 56%. Index Terms — design guarantee inferring, correlation extraction, interconnect matching, H-tree optimization I.

ℓ1-regularized logistic regression, also known as sparse logistic regression, is widely used in machine learning, computer vision, data mining, bioinformatics and neural signal processing. The use of ℓ1 regularization attributes attractive properties to the classifier, such as feature selection, robustness to noise, and as a result, classifier generality in the context of supervised learning. When a sparse logistic regression problem has large-scale data in high dimensions, it is computationally expensive to minimize the non-differentiable ℓ1-norm in the objective function. Motivated by recent work (Koh et al., 2007; Hale et al., 2008), we propose a novel hybrid algorithm based on combining two types of optimization iterations: one being very fast and memory friendly while the other being slower but more accurate. Called hybrid iterative shrinkage (HIS), the resulting algorithm is comprised of a fixed point continuation phase and an interior point phase. The first phase is based completely on memory efficient operations such as matrix-vector multiplications, while the second phase is based on a truncated Newton’s method. Furthermore, we show that various optimization techniques, including line search and continuation, can significantly accelerate convergence. The algorithm has global convergence at a geometric rate (a Q-linear rate in optimization terminology).