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Fast Arithmetic for PublicKey Algorithms in Galois Field with Composite Exponents
 IEEE Transaction of Computers
, 1999
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Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
 In Workshop on Cryptographic Hardware and Embedded Systems (CHES2001
, 2001
"... Abstract. We explore the use of subfield arithmetic for efficient implementations of Galois Field arithmetic especially in the context of the Rijndael block cipher. Our technique involves mapping field elements to a composite field representation. We describe how to select a representation which m ..."
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Cited by 28 (1 self)
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Abstract. We explore the use of subfield arithmetic for efficient implementations of Galois Field arithmetic especially in the context of the Rijndael block cipher. Our technique involves mapping field elements to a composite field representation. We describe how to select a representation which minimizes the computation cost of the relevant arithmetic, taking into account the cost of the mapping as well. Our method results in a very compact and fast gate circuit for Rijndael encryption. In conjunction with bitslicing techniques applied to newly proposed parallelizable modes of operation, our circuit leads to a highperformance software implementation for Rijndael encryption which offers significant speedup compared to previously reported implementations.
A SuperSerial Galois Fields Multiplier for FPGAs and its Application to PublicKey Algorithms
 In Seventh Annual IEEE Symposium on FieldProgrammable Custom Computing Machines, FCCM '99
, 1999
"... This contribution introduces a scalable multiplier architecture for Galois field GF (2 k ) amenable for field programmable gate arrays (FPGAs) implementations. This architecture is well suited for the implementation of publickey cryptosystems which require programmable multipliers in large Galois ..."
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Cited by 14 (2 self)
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This contribution introduces a scalable multiplier architecture for Galois field GF (2 k ) amenable for field programmable gate arrays (FPGAs) implementations. This architecture is well suited for the implementation of publickey cryptosystems which require programmable multipliers in large Galois fields. The architecture trades a reduction in resources with an increase in the number of clock cycles. This architecture is also fine grain scalable in both the time and the area (or logic) dimensions thus facilitating implementations that maximize their use of finite FPGA resources while achieving fast computational speed. This leads to an architecture that requires less resources than traditional bit serial multipliers, which we demonstrated with implementations of multipliers in the field GF (2 167 ). Our results demonstrate that for this field one can realize superserial multipliers that use 2.76 times fewer function generators and 6.84 times fewer flipflops than their serial mult...
Implementation Options for Finite Fields Arithmetic for Elliptic Curve Cryptosystems
 Proc. of 3rd Workshop on Elliptic Curve Cryptosystems, ECC '99
, 1999
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Efficient Implementation of Rijndael Encryption With Composite Field Arithmetic
"... We explore the use of subfield arithmetic for efficient implementations Galois Field arithmetic in the context of Rijndael cipher. ..."
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Cited by 8 (2 self)
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We explore the use of subfield arithmetic for efficient implementations Galois Field arithmetic in the context of Rijndael cipher.
Efficient Galois Field Arithmetic on SIMD Architectures
"... We propose techniques to utilize the data parallelism capabilities of a SIMD architecture in computations involving Galois Field arithmetic. Galois Field arithmetic nds wide use in engineering applications, including errorcorrecting codes and cryptography. Often these applications involve exten ..."
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Cited by 4 (0 self)
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We propose techniques to utilize the data parallelism capabilities of a SIMD architecture in computations involving Galois Field arithmetic. Galois Field arithmetic nds wide use in engineering applications, including errorcorrecting codes and cryptography. Often these applications involve extensive arithmetic on small (8bit) numbers, and straightforward implementations may highly underutilize the wideword capabilities of a SIMD processor.
On the Circuit Complexity of Isomorphic Galois Field Transformations
"... We study the circuit complexity of linear transformations between Galois fields GF(2 and their isomorphic composite fields GF((2 ). For such a transformation, we show a lower bound of mn) on the number of gates required in any circuit consisting of constantfanin XOR gates, except for a class of tr ..."
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Cited by 1 (0 self)
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We study the circuit complexity of linear transformations between Galois fields GF(2 and their isomorphic composite fields GF((2 ). For such a transformation, we show a lower bound of mn) on the number of gates required in any circuit consisting of constantfanin XOR gates, except for a class of transformations between representations of such fields which are nicely characterized. The exceptions show that the polynomials representing the fields must be of a regular form, which may be of independent interest. We characterize a family of transformations which can be implemented as crosswires (permutations), without using any gates, which is very useful in designing hardware implementations  and through bitslicing, software implementations  of computations based on Galois Field arithmetic. We also show that our lower bound is tight, by demonstrating a class of transformations which only require a linear number of gates.
An Architecture for a Compact AES System
"... This paper describes a compact architecture developed for the Rijndael ciphering system. The mathematical manipulation lies on finite field computation where the element inversion is performed using the composite field technique. The resulted Sbox development is ideal for applications where table l ..."
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This paper describes a compact architecture developed for the Rijndael ciphering system. The mathematical manipulation lies on finite field computation where the element inversion is performed using the composite field technique. The resulted Sbox development is ideal for applications where table lookup is not applicable or restricted. The overall proposed architecture is also suitable for a highly paralleled computation scheme where data flow can be arranged in pipeline manner. For the areasaving implementation, the inversion block and the key scheduling circuits could be shared by both encryption and decryption.
VLSI Implementation of an AES Algorithm Resistant to Differential Power Analysis Attack
"... AbstractThis paper proposes a low cost VLSI implementation of a masked AES algorithm resistant to DPA (Differential Power Analysis) attack. In order to minimize the influence of the modification to the hardware cost while enabling it resistant to DPA, such methods as altering calculation order, mod ..."
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AbstractThis paper proposes a low cost VLSI implementation of a masked AES algorithm resistant to DPA (Differential Power Analysis) attack. In order to minimize the influence of the modification to the hardware cost while enabling it resistant to DPA, such methods as altering calculation order, module reuse and composite field computation are employed to reduce chip area and maintain its speed. Using the HHNEC 0.25ȝm CMOS process, the scale of the design is about 48K equivalent gates and its system frequency is up to 70MHz. The throughput of the 128bit data encryption and decryption are as high as 380Mbit/s. I.