The implementation of advanced channel receivers using low-end multimedia instruction set processors is a productive, flexible and cost effective alternative to custom hardware.

In the age of highly integrated system LSIs, design methodologies for shorter time-to-market and higher reprogrammability after the chip fabrications are now key research issues because of the difficulty of complete verification before tape-out of LSI designs. In this paper, we first introduce a IP-based VLSI architecture that consists of a main processor and an additional hardware (both custom hard macros and FPGA on a single chip) specialized to be in charge of the specific instructions. We further replace the controller circuits of the specialized hardware with compact micro-controllers and memories by using IP libraries (hard macros), which results in the increase of the debuggability and the flexibility of design even for computations realized by hard macros. We call the proposed architecture as Field Modifiable Architecture (FMA). Experimental results confirm that our architecture can achieve significant performance improvement in terms of execution cycles and that EC (Engineering Change) can be successfully accommodated “after ” chip fabrications. 1

In this work we illustrates the strong interaction between the data organisation in background memory and the data format required for sub-word level acceleration. The impact of such interaction is demonstrated on the implementation of a Digital Audio Broadcast Channel Decoder on a TriMedia processor, where data format transformations applied on the background memory data enable a substantially better exploitation of the available Single Instruction Multiple Data instructions. As a result, a factor two reduction for both execution time and data memory energy is achieved.