There is a conflict between the goals of improving the quality of scientific software and improving its performance. A key issue is to support reuse and re-assembly of sophisticated software components without compromising performance. This paper describes THEMIS, a programming model and run time library being designed to support cross-component performance optimisation through explicit manipulation of the computation’s iteration space at run-time. Each component is augmented with “component dependence metadata”, which characterises the constraints on its execution order, data distribution and memory access order. We show how this supports dynamic adaptation of each component to exploit the available resources, the context in which its operands are generated, and results are used, and the evolution of the problem instance. Using a computational fluid dynamics visualisation example as motivation, we show how component dependence metadata provides a framework in which a number of interesting optimisations become possible. Examples include data placement optimisation, loop fusion, tiling, memoisation, checkpointing and incrementalisation. 1

Constructive methods for parallel programming are characterised by the composition of optimised, parallel software components. This paper concerns data placement, a key cross-component optimisation for regular data-parallel programs.

In this paper, we introduce a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The investigated class of computer architectures can be described by massively parallel networked processing elements that, using today’s hardware technology, may be implemented on a single chip (SoC – System on a Chip). Existing approaches for mapping computational-intensive algorithms to parallel architectures either consider the implementation in dedicated hardware or the implementation on a given supercomputer. Many intermediate solutions between these extremes are coming up ranging from finegrained FPGAs to coarse-grained processor arrays. For these architectures, we propose in this contribution a codesign approach in the sense of designing special purpose parallel processor architectures and efficient mapping tools simultaneously.

The current microarchitecture trend leads toward heterogeneity. This evolution is driven by the end of Moore’s law and the frequency wall due to the power wall. Moreover, with the spreading of smartphone, some constraints from the mobile world drive the design of most new architectures. An immediate consequence is that an application has to be executable on various targets. Porting and maintaining multiple versions of the code base requires different skills and the efforts required in the process as well as the increased complexity in debugging and testing are time consuming, thus expensive. Some solutions based on compilers emerge. They are based either on directives added to C like in openhmpp or openacc or on automatic solution like pocc, Pluto, ppcg, or Par4All. However compilers cannot retarget in an efficient way any program written in a low-level language such as unconstrained C. Programmers should follow good practices when writing code so that compilers have more room to perform the transformations required for efficient execution on heterogeneous targets.