Results 1  10
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11
Exact Coloring of RealLife Graphs is Easy
 DAC '97
, 1997
"... Graph coloring has several important applications in VLSI CAD. Since graph coloring is NPcomplete, heuristics are used to approximate the optimum solution. But heuristic solutions are typically 10% off, and as muchas 100% off, the minimum coloring. This paper shows that since reallife graphs appe ..."
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Cited by 28 (0 self)
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Graph coloring has several important applications in VLSI CAD. Since graph coloring is NPcomplete, heuristics are used to approximate the optimum solution. But heuristic solutions are typically 10% off, and as muchas 100% off, the minimum coloring. This paper shows that since reallife graphs appear to be 1perfect, one can indeed solve them exactly for a small overhead.
Algorithmic aspects of three dimensional mcm routing
 in Proceedings of the ACM/IEEE Design Automation Conference
, 1994
"... Abstract In this paper, we present a new routing approach for MCMs in which the routing space is partitioned into several towers. The routing is carried out in three steps. In the rst step, the routing density is uniformly distributed over the three dimensional routing space. In the next step, the ..."
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Cited by 9 (0 self)
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Abstract In this paper, we present a new routing approach for MCMs in which the routing space is partitioned into several towers. The routing is carried out in three steps. In the rst step, the routing density is uniformly distributed over the three dimensional routing space. In the next step, the exact locations of nets on the faces of each tower are determined. Finally, the exact paths for the nets in each tower are determined and routed. Unlike the traditional MCM routing which converts the three dimensional routing problem into a set of two dimensional routing problems, our approach decomposes the problem into a set of smaller, yet three dimensional tower routing problems. Experimental results show the validity of our methodology. 1
ABSTRACT Constraint Driven I/O Planning and Placement for Chippackage Codesign ∗
"... Systemonchip and systeminpackage result in increased number of I/O cells and complicated constraints for both chip designs and package designs. This renders the traditional manually tuned and chipcentered I/O designs suboptimal in terms of both turn around time and design quality. In this paper ..."
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Cited by 4 (1 self)
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Systemonchip and systeminpackage result in increased number of I/O cells and complicated constraints for both chip designs and package designs. This renders the traditional manually tuned and chipcentered I/O designs suboptimal in terms of both turn around time and design quality. In this paper we formally introduce a set of design constraints suitable for chippackage codesign. We formulate a constraintdriven I/O planning and placement problem, and solve it by a multistep algorithm based upon integer linear programming. Experiment results using real industry designs show that the proposed algorithm can effectively find a large scale I/O placement solution and satisfy all given design constraints in less than 10 minutes. In contrast, the stateoftheart without considering those design constraints simply cannot meet all design constraints by relying solely upon the conventional iterative approach. 1.
TEG: A New PostLayout Optimization Method
 Proc. ISPD 2002
"... Postlayout is an important stage in the modern VLSI design. With the completed detail routing, it is the only stage where extraction and veri¯cation tools can get accurate results for further optimization. But the problem is that design optimization or modi¯cation are very hard to perform in the ..."
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Postlayout is an important stage in the modern VLSI design. With the completed detail routing, it is the only stage where extraction and veri¯cation tools can get accurate results for further optimization. But the problem is that design optimization or modi¯cation are very hard to perform in the postlayout stage, because most layout elements are under tight geometry constraints due to the routing. In this paper we propose a new method to resolve this problem, named TEG. Based on an improved topological layout representation and a set of layout operation algorithms, TEG provides an incremental layout modi¯cation environment for the postlayout applications. Experimental results showed that TEG was e±cient and e®ective in processing industry VLSI designs. 1.
A probabilistic constructive approach to optimization problems
 in ACM/IEEE ICCAD, 2001
, 2001
"... We propose a new optimization paradigm for solving intractable combinatorial problems. The technique, named Probabilistic Constructive (PC), combines the advantages of both constructive and probabilistic algorithms. The constructive aspect provides relatively short runtime and makes the technique am ..."
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Cited by 2 (2 self)
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We propose a new optimization paradigm for solving intractable combinatorial problems. The technique, named Probabilistic Constructive (PC), combines the advantages of both constructive and probabilistic algorithms. The constructive aspect provides relatively short runtime and makes the technique amenable for the inclusion of insights through heuristic rules. The probabilistic nature facilitates a flexible tradeoff between runtime and the quality of solution. In addition to presenting the generic technique, we apply it to the Maximal Independent Set problem. Extensive experimentation indicates that the new approach provides very attractive tradeoffs between the quality of the solution and runtime, often outperforming the best previously published approaches. 1.
A provably good global routing algorithm in multilayer IC and MCM layout designs, manuscript
"... Given a multilayer routing area, we consider the global routing problem of selecting a maximum set of nets, such that every net can be routed entirely in one of the given layers without violating the physical capacity constraints. This problem is motivated by applications in multilayer IC and multi ..."
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Given a multilayer routing area, we consider the global routing problem of selecting a maximum set of nets, such that every net can be routed entirely in one of the given layers without violating the physical capacity constraints. This problem is motivated by applications in multilayer IC and multichip module (MCM) layout designs. The contribution of this paper is threefold. First, we formulate the problem as an integer linear program (ILP). Second, we modify an algorithm by Garg and Könemann for packing linear programs to obtain an approximation algorithm for the global routing problem. Our algorithm provides solutions guaranteed to be within a certain range of the global optimal solution, and runs in polynomialtime even if all, possibly exponentially many, Steiner trees are considered in the formulation. Finally, we demonstrate that the complexity of our algorithm can be significantly reduced in the case of identical routing layers.
Algorithmic Aspects of Three Dimensional MCM Routing
"... Abstract In this paper, we present a new routing approach for MCMs in which the routing space is partitioned into several towers. The routing is carried out in three steps. In the rst step, the routing density is uniformly distributed over the three dimensional routing space. In the next step, the ..."
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Abstract In this paper, we present a new routing approach for MCMs in which the routing space is partitioned into several towers. The routing is carried out in three steps. In the rst step, the routing density is uniformly distributed over the three dimensional routing space. In the next step, the exact locations of nets on the faces of each tower are determined. Finally, the exact paths for the nets in each tower are determined and routed. Unlike the traditional MCM routing which converts the three dimensional routing problem into a set of two dimensional routing problems, our approach decomposes the problem into a set of smaller, yet three dimensional tower routing problems. Experimental results show the validity of our methodology. 1
Abstract Exact Coloring of RealLife Graphs is Easy
"... coloring has several important applications in VLSI CAD. Since graph coloring is NPcomplete, heuristics are used to approximate the optimum solution. But heuristic solutions are typically 10 % o, and as much as 100 % o, the minimum coloring. This paper shows that since reallife graphs appear to be ..."
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coloring has several important applications in VLSI CAD. Since graph coloring is NPcomplete, heuristics are used to approximate the optimum solution. But heuristic solutions are typically 10 % o, and as much as 100 % o, the minimum coloring. This paper shows that since reallife graphs appear to be 1perfect, one can indeed solve them exactly for a small overhead. 1
NonParametric Statistical Techniques for Computational Forensic Engineering
"... Computational forensic engineering is the process of identification of the tool or algorithm that was used to produce a particular output or solution by examining the structural properties of the output. We introduce a new Relative Generic Forensic Engineering (RGFE)technique that has several advant ..."
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Computational forensic engineering is the process of identification of the tool or algorithm that was used to produce a particular output or solution by examining the structural properties of the output. We introduce a new Relative Generic Forensic Engineering (RGFE)technique that has several advantages over the previously proposed approaches. From the quantitative point of view, the new RGFE technique performs not only more accurate identification of the tool used but also provides the identification with a level of confidence. A higher degree of classification is achieved by our technique with the ability to identify the output as produced by an unknown tool. We introduce a generic formulation which enables rapid application of the RGFE approach to a variety of problems that can be formulated as 01 integer linear programs. Additionally, we present forensic engineering scenarios which enable a natural classification of the forensic engineering task with respect to the types and amount of information available to conduct the classification. From the technical point of view, the key innovations of the RGFE technique include the development of a simulated annealingbased CART classification and clustering technique and a generic property formulation technique which provides a systematic way to develop properties for a given problem or facilitates their reuse. In addition to solution properties, we introduce instance properties which enable an enhanced classification of problem instances leading to a higher accuracy of algorithm identification. Finally, the single most important innovation, property calibration, interprets the value for a given algorithm for a given property relative to the values for other algorithms. We demonstrated the RGFE technique on two canonical optimization problems: boolean satisfiability (SAT)and graph coloring (GC) and used statistical techniques to establish the effectiveness of the approach.
Fast Pad Redistribution from PeripheryIO to AreaIO
 in Proc. IEEE MultiChip Module Conf
, 1994
"... The problem of redistributing IO from bondpads on the periphery of an IC to an array of solder bumps occurs frequently in MCM layout. We show that the commonly held belief that providing enough escapes at the perimeter of the array is not sufficient to guarantee routability of the design. We analyze ..."
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The problem of redistributing IO from bondpads on the periphery of an IC to an array of solder bumps occurs frequently in MCM layout. We show that the commonly held belief that providing enough escapes at the perimeter of the array is not sufficient to guarantee routability of the design. We analyze the Even Wiring Distribution (EWD) routing heuristic and show that it produces designs whose critical wire density is no greater that p 2 times the best possible design. Then, we employ the bound on EWD to establish a surprisingly nonmonotonic relationship between bump pitch and design routability, and present our implementation of a design system that employs these principles. 1 Introduction The problem of fanningout solder bump arrays occurs frequently in MCM layout. As array bonding for bare die becomes more prevalent, the frequency with which these fanin/fanout problems need to be solved will increase. At the same time, the trend of increasing IO per chip will increase the amount...